From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h
Date: Thu, 20 Oct 2022 19:00:20 +0300 [thread overview]
Message-ID: <20221020160022.1823365-3-imre.deak@intel.com> (raw)
In-Reply-To: <20221020160022.1823365-1-imre.deak@intel.com>
An upcoming patch moves the DKL PHY register definitions to
intel_dkl_phy_regs.h, so for consistency rename intel_tc_phy_regs.h
containing only MG PHY register definitions to intel_mg_phy_regs.h.
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
.../display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h} | 6 +++---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
rename drivers/gpu/drm/i915/display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h} (99%)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7708ccbbdeb75..37272c6e4269d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -56,13 +56,13 @@
#include "intel_hdmi.h"
#include "intel_hotplug.h"
#include "intel_lspcon.h"
+#include "intel_mg_phy_regs.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_snps_phy.h"
#include "intel_sprite.h"
#include "intel_tc.h"
-#include "intel_tc_phy_regs.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
#include "skl_scaler.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 58e5c6f7de750..38d686389e1bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -29,9 +29,9 @@
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_dpll_mgr.h"
+#include "intel_mg_phy_regs.h"
#include "intel_pch_refclk.h"
#include "intel_tc.h"
-#include "intel_tc_phy_regs.h"
/**
* DOC: Display PLLs
diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
similarity index 99%
rename from drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
rename to drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
index 5a545086f9599..07978f8d5fb74 100644
--- a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
@@ -3,8 +3,8 @@
* Copyright © 2022 Intel Corporation
*/
-#ifndef __INTEL_TC_PHY_REGS__
-#define __INTEL_TC_PHY_REGS__
+#ifndef __INTEL_MG_PHY_REGS__
+#define __INTEL_MG_PHY_REGS__
#include "i915_reg_defs.h"
@@ -277,4 +277,4 @@
_MG_PLL_TDC_COLDST_BIAS_PORT1, \
_MG_PLL_TDC_COLDST_BIAS_PORT2)
-#endif /* __INTEL_TC_PHY_REGS__ */
+#endif /* __INTEL_MG_PHY_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8cecd41ed0033..351709725cd04 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -9,8 +9,8 @@
#include "intel_display_power_map.h"
#include "intel_display_types.h"
#include "intel_dp_mst.h"
+#include "intel_mg_phy_regs.h"
#include "intel_tc.h"
-#include "intel_tc_phy_regs.h"
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
--
2.37.1
next prev parent reply other threads:[~2022-10-20 16:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 16:00 [Intel-gfx] [PATCH v2 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses Imre Deak
2022-10-20 16:00 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses Imre Deak
2022-10-20 16:00 ` Imre Deak
2022-10-20 16:00 ` Imre Deak [this message]
2022-10-20 16:00 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Imre Deak
2022-10-20 16:00 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions Imre Deak
2022-10-20 17:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses Patchwork
2022-10-20 17:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-20 18:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-20 23:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-21 8:26 ` [Intel-gfx] [PATCH v2 0/4] " Jani Nikula
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