* [PATCH v1 1/3] update-linux-headers: Version 6.1-rc2
2022-10-27 5:46 [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions Mayuresh Chitale
@ 2022-10-27 5:46 ` Mayuresh Chitale
2022-10-27 5:46 ` [PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions Mayuresh Chitale
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Mayuresh Chitale @ 2022-10-27 5:46 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis
Sync headers with kernel commit 247f34f7b803
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
include/standard-headers/drm/drm_fourcc.h | 34 ++++-
include/standard-headers/linux/ethtool.h | 63 +++++++-
include/standard-headers/linux/fuse.h | 6 +-
.../linux/input-event-codes.h | 1 +
include/standard-headers/linux/virtio_blk.h | 19 +++
| 26 ++--
| 2 +
| 2 +
| 4 +
| 1 +
| 14 ++
| 4 +
| 142 ++++++++++++++++++
13 files changed, 298 insertions(+), 20 deletions(-)
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h
index 48b620cbef..b868488f93 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -98,18 +98,42 @@ extern "C" {
#define DRM_FORMAT_INVALID 0
/* color index */
+#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
+#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
+#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
-/* 8 bpp Red */
+/* 1 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
+
+/* 2 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
+
+/* 4 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
+
+/* 8 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
+
+/* 1 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
+
+/* 2 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
+
+/* 4 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
+
+/* 8 bpp Red (direct relationship between channel value and brightness) */
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
-/* 10 bpp Red */
+/* 10 bpp Red (direct relationship between channel value and brightness) */
#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
-/* 12 bpp Red */
+/* 12 bpp Red (direct relationship between channel value and brightness) */
#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
-/* 16 bpp Red */
+/* 16 bpp Red (direct relationship between channel value and brightness) */
#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
/* 16 bpp RG */
@@ -204,7 +228,9 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h
index 4537da20cc..1dc56cdc0a 100644
--- a/include/standard-headers/linux/ethtool.h
+++ b/include/standard-headers/linux/ethtool.h
@@ -736,6 +736,51 @@ enum ethtool_module_power_mode {
ETHTOOL_MODULE_POWER_MODE_HIGH,
};
+/**
+ * enum ethtool_podl_pse_admin_state - operational state of the PoDL PSE
+ * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
+ * @ETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN: state of PoDL PSE functions are
+ * unknown
+ * @ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED: PoDL PSE functions are disabled
+ * @ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED: PoDL PSE functions are enabled
+ */
+enum ethtool_podl_pse_admin_state {
+ ETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1,
+ ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED,
+ ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED,
+};
+
+/**
+ * enum ethtool_podl_pse_pw_d_status - power detection status of the PoDL PSE.
+ * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN: PoDL PSE
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED: "The enumeration “disabled” is
+ * asserted true when the PoDL PSE state diagram variable mr_pse_enable is
+ * false"
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING: "The enumeration “searching” is
+ * asserted true when either of the PSE state diagram variables
+ * pi_detecting or pi_classifying is true."
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING: "The enumeration “deliveringPower”
+ * is asserted true when the PoDL PSE state diagram variable pi_powered is
+ * true."
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP: "The enumeration “sleep” is asserted
+ * true when the PoDL PSE state diagram variable pi_sleeping is true."
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_IDLE: "The enumeration “idle” is asserted true
+ * when the logical combination of the PoDL PSE state diagram variables
+ * pi_prebiased*!pi_sleeping is true."
+ * @ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR: "The enumeration “error” is asserted
+ * true when the PoDL PSE state diagram variable overload_held is true."
+ */
+enum ethtool_podl_pse_pw_d_status {
+ ETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1,
+ ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED,
+ ETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING,
+ ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING,
+ ETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP,
+ ETHTOOL_PODL_PSE_PW_D_STATUS_IDLE,
+ ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR,
+};
+
/**
* struct ethtool_gstrings - string set for data tagging
* @cmd: Command number = %ETHTOOL_GSTRINGS
@@ -1840,6 +1885,20 @@ static inline int ethtool_validate_duplex(uint8_t duplex)
#define MASTER_SLAVE_STATE_SLAVE 3
#define MASTER_SLAVE_STATE_ERR 4
+/* These are used to throttle the rate of data on the phy interface when the
+ * native speed of the interface is higher than the link speed. These should
+ * not be used for phy interfaces which natively support multiple speeds (e.g.
+ * MII or SGMII).
+ */
+/* No rate matching performed. */
+#define RATE_MATCH_NONE 0
+/* The phy sends pause frames to throttle the MAC. */
+#define RATE_MATCH_PAUSE 1
+/* The phy asserts CRS to prevent the MAC from transmitting. */
+#define RATE_MATCH_CRS 2
+/* The MAC is programmed with a sufficiently-large IPG. */
+#define RATE_MATCH_OPEN_LOOP 3
+
/* Which connector port. */
#define PORT_TP 0x00
#define PORT_AUI 0x01
@@ -2033,8 +2092,8 @@ enum ethtool_reset_flags {
* reported consistently by PHYLIB. Read-only.
* @master_slave_cfg: Master/slave port mode.
* @master_slave_state: Master/slave port state.
+ * @rate_matching: Rate adaptation performed by the PHY
* @reserved: Reserved for future use; see the note on reserved space.
- * @reserved1: Reserved for future use; see the note on reserved space.
* @link_mode_masks: Variable length bitmaps.
*
* If autonegotiation is disabled, the speed and @duplex represent the
@@ -2085,7 +2144,7 @@ struct ethtool_link_settings {
uint8_t transceiver;
uint8_t master_slave_cfg;
uint8_t master_slave_state;
- uint8_t reserved1[1];
+ uint8_t rate_matching;
uint32_t reserved[7];
uint32_t link_mode_masks[];
/* layout of link_mode_masks fields:
diff --git a/include/standard-headers/linux/fuse.h b/include/standard-headers/linux/fuse.h
index bda06258be..713d259768 100644
--- a/include/standard-headers/linux/fuse.h
+++ b/include/standard-headers/linux/fuse.h
@@ -194,6 +194,9 @@
* - add FUSE_SECURITY_CTX init flag
* - add security context to create, mkdir, symlink, and mknod requests
* - add FUSE_HAS_INODE_DAX, FUSE_ATTR_DAX
+ *
+ * 7.37
+ * - add FUSE_TMPFILE
*/
#ifndef _LINUX_FUSE_H
@@ -225,7 +228,7 @@
#define FUSE_KERNEL_VERSION 7
/** Minor version number of this interface */
-#define FUSE_KERNEL_MINOR_VERSION 36
+#define FUSE_KERNEL_MINOR_VERSION 37
/** The node ID of the root inode */
#define FUSE_ROOT_ID 1
@@ -533,6 +536,7 @@ enum fuse_opcode {
FUSE_SETUPMAPPING = 48,
FUSE_REMOVEMAPPING = 49,
FUSE_SYNCFS = 50,
+ FUSE_TMPFILE = 51,
/* CUSE specific operations */
CUSE_INIT = 4096,
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
index 50790aee5a..815f7a1dff 100644
--- a/include/standard-headers/linux/input-event-codes.h
+++ b/include/standard-headers/linux/input-event-codes.h
@@ -862,6 +862,7 @@
#define ABS_TOOL_WIDTH 0x1c
#define ABS_VOLUME 0x20
+#define ABS_PROFILE 0x21
#define ABS_MISC 0x28
diff --git a/include/standard-headers/linux/virtio_blk.h b/include/standard-headers/linux/virtio_blk.h
index 2dcc90826a..e81715cd70 100644
--- a/include/standard-headers/linux/virtio_blk.h
+++ b/include/standard-headers/linux/virtio_blk.h
@@ -40,6 +40,7 @@
#define VIRTIO_BLK_F_MQ 12 /* support more than one vq */
#define VIRTIO_BLK_F_DISCARD 13 /* DISCARD is supported */
#define VIRTIO_BLK_F_WRITE_ZEROES 14 /* WRITE ZEROES is supported */
+#define VIRTIO_BLK_F_SECURE_ERASE 16 /* Secure Erase is supported */
/* Legacy feature bits */
#ifndef VIRTIO_BLK_NO_LEGACY
@@ -119,6 +120,21 @@ struct virtio_blk_config {
uint8_t write_zeroes_may_unmap;
uint8_t unused1[3];
+
+ /* the next 3 entries are guarded by VIRTIO_BLK_F_SECURE_ERASE */
+ /*
+ * The maximum secure erase sectors (in 512-byte sectors) for
+ * one segment.
+ */
+ __virtio32 max_secure_erase_sectors;
+ /*
+ * The maximum number of secure erase segments in a
+ * secure erase command.
+ */
+ __virtio32 max_secure_erase_seg;
+ /* Secure erase commands must be aligned to this number of sectors. */
+ __virtio32 secure_erase_sector_alignment;
+
} QEMU_PACKED;
/*
@@ -153,6 +169,9 @@ struct virtio_blk_config {
/* Write zeroes command */
#define VIRTIO_BLK_T_WRITE_ZEROES 13
+/* Secure erase command */
+#define VIRTIO_BLK_T_SECURE_ERASE 14
+
#ifndef VIRTIO_BLK_NO_LEGACY
/* Barrier before this op. */
#define VIRTIO_BLK_T_BARRIER 0x80000000
--git a/linux-headers/asm-generic/hugetlb_encode.h b/linux-headers/asm-generic/hugetlb_encode.h
index 4f3d5aaa11..de687009bf 100644
--- a/linux-headers/asm-generic/hugetlb_encode.h
+++ b/linux-headers/asm-generic/hugetlb_encode.h
@@ -20,18 +20,18 @@
#define HUGETLB_FLAG_ENCODE_SHIFT 26
#define HUGETLB_FLAG_ENCODE_MASK 0x3f
-#define HUGETLB_FLAG_ENCODE_16KB (14 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_64KB (16 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_512KB (19 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_1MB (20 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_2MB (21 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_8MB (23 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_16MB (24 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_32MB (25 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_256MB (28 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_512MB (29 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_1GB (30 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_2GB (31 << HUGETLB_FLAG_ENCODE_SHIFT)
-#define HUGETLB_FLAG_ENCODE_16GB (34 << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_16KB (14U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_64KB (16U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_512KB (19U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_1MB (20U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_2MB (21U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_8MB (23U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_16MB (24U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_32MB (25U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_256MB (28U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_512MB (29U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_1GB (30U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_2GB (31U << HUGETLB_FLAG_ENCODE_SHIFT)
+#define HUGETLB_FLAG_ENCODE_16GB (34U << HUGETLB_FLAG_ENCODE_SHIFT)
#endif /* _ASM_GENERIC_HUGETLB_ENCODE_H_ */
--git a/linux-headers/asm-generic/mman-common.h b/linux-headers/asm-generic/mman-common.h
index 6c1aa92a92..6ce1f1ceb4 100644
--- a/linux-headers/asm-generic/mman-common.h
+++ b/linux-headers/asm-generic/mman-common.h
@@ -77,6 +77,8 @@
#define MADV_DONTNEED_LOCKED 24 /* like DONTNEED, but drop locked pages too */
+#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
+
/* compatibility flags */
#define MAP_FILE 0
--git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h
index 1be428663c..c6e1fc77c9 100644
--- a/linux-headers/asm-mips/mman.h
+++ b/linux-headers/asm-mips/mman.h
@@ -103,6 +103,8 @@
#define MADV_DONTNEED_LOCKED 24 /* like DONTNEED, but drop locked pages too */
+#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
+
/* compatibility flags */
#define MAP_FILE 0
--git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
index 7351417afd..8985ff234c 100644
--- a/linux-headers/asm-riscv/kvm.h
+++ b/linux-headers/asm-riscv/kvm.h
@@ -48,6 +48,7 @@ struct kvm_sregs {
/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_config {
unsigned long isa;
+ unsigned long zicbom_block_size;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
@@ -98,6 +99,9 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_M,
KVM_RISCV_ISA_EXT_SVPBMT,
KVM_RISCV_ISA_EXT_SSTC,
+ KVM_RISCV_ISA_EXT_SVINVAL,
+ KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
+ KVM_RISCV_ISA_EXT_ZICBOM,
KVM_RISCV_ISA_EXT_MAX,
};
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index ebdafa576d..b2783c5202 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1175,6 +1175,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_VM_DISABLE_NX_HUGE_PAGES 220
#define KVM_CAP_S390_ZPCI_OP 221
#define KVM_CAP_S390_CPU_TOPOLOGY 222
+#define KVM_CAP_DIRTY_LOG_RING_ACQ_REL 223
#ifdef KVM_CAP_IRQ_ROUTING
--git a/linux-headers/linux/psci.h b/linux-headers/linux/psci.h
index 213b2a0f70..e60dfd8907 100644
--- a/linux-headers/linux/psci.h
+++ b/linux-headers/linux/psci.h
@@ -48,12 +48,26 @@
#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
#define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10)
+#define PSCI_1_0_FN_CPU_FREEZE PSCI_0_2_FN(11)
+#define PSCI_1_0_FN_CPU_DEFAULT_SUSPEND PSCI_0_2_FN(12)
+#define PSCI_1_0_FN_NODE_HW_STATE PSCI_0_2_FN(13)
#define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14)
#define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15)
+#define PSCI_1_0_FN_STAT_RESIDENCY PSCI_0_2_FN(16)
+#define PSCI_1_0_FN_STAT_COUNT PSCI_0_2_FN(17)
+
#define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18)
+#define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19)
+#define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(19)
+#define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12)
+#define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13)
#define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14)
+#define PSCI_1_0_FN64_STAT_RESIDENCY PSCI_0_2_FN64(16)
+#define PSCI_1_0_FN64_STAT_COUNT PSCI_0_2_FN64(17)
+
#define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18)
+#define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(19)
/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff
--git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
index a3a377cd44..ba5d0df52f 100644
--- a/linux-headers/linux/userfaultfd.h
+++ b/linux-headers/linux/userfaultfd.h
@@ -12,6 +12,10 @@
#include <linux/types.h>
+/* ioctls for /dev/userfaultfd */
+#define USERFAULTFD_IOC 0xAA
+#define USERFAULTFD_IOC_NEW _IO(USERFAULTFD_IOC, 0x00)
+
/*
* If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and
* UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In
--git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
index ede44b5572..bee7e42198 100644
--- a/linux-headers/linux/vfio.h
+++ b/linux-headers/linux/vfio.h
@@ -986,6 +986,148 @@ enum vfio_device_mig_state {
VFIO_DEVICE_STATE_RUNNING_P2P = 5,
};
+/*
+ * Upon VFIO_DEVICE_FEATURE_SET, allow the device to be moved into a low power
+ * state with the platform-based power management. Device use of lower power
+ * states depends on factors managed by the runtime power management core,
+ * including system level support and coordinating support among dependent
+ * devices. Enabling device low power entry does not guarantee lower power
+ * usage by the device, nor is a mechanism provided through this feature to
+ * know the current power state of the device. If any device access happens
+ * (either from the host or through the vfio uAPI) when the device is in the
+ * low power state, then the host will move the device out of the low power
+ * state as necessary prior to the access. Once the access is completed, the
+ * device may re-enter the low power state. For single shot low power support
+ * with wake-up notification, see
+ * VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP below. Access to mmap'd
+ * device regions is disabled on LOW_POWER_ENTRY and may only be resumed after
+ * calling LOW_POWER_EXIT.
+ */
+#define VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY 3
+
+/*
+ * This device feature has the same behavior as
+ * VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY with the exception that the user
+ * provides an eventfd for wake-up notification. When the device moves out of
+ * the low power state for the wake-up, the host will not allow the device to
+ * re-enter a low power state without a subsequent user call to one of the low
+ * power entry device feature IOCTLs. Access to mmap'd device regions is
+ * disabled on LOW_POWER_ENTRY_WITH_WAKEUP and may only be resumed after the
+ * low power exit. The low power exit can happen either through LOW_POWER_EXIT
+ * or through any other access (where the wake-up notification has been
+ * generated). The access to mmap'd device regions will not trigger low power
+ * exit.
+ *
+ * The notification through the provided eventfd will be generated only when
+ * the device has entered and is resumed from a low power state after
+ * calling this device feature IOCTL. A device that has not entered low power
+ * state, as managed through the runtime power management core, will not
+ * generate a notification through the provided eventfd on access. Calling the
+ * LOW_POWER_EXIT feature is optional in the case where notification has been
+ * signaled on the provided eventfd that a resume from low power has occurred.
+ */
+struct vfio_device_low_power_entry_with_wakeup {
+ __s32 wakeup_eventfd;
+ __u32 reserved;
+};
+
+#define VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP 4
+
+/*
+ * Upon VFIO_DEVICE_FEATURE_SET, disallow use of device low power states as
+ * previously enabled via VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY or
+ * VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP device features.
+ * This device feature IOCTL may itself generate a wakeup eventfd notification
+ * in the latter case if the device had previously entered a low power state.
+ */
+#define VFIO_DEVICE_FEATURE_LOW_POWER_EXIT 5
+
+/*
+ * Upon VFIO_DEVICE_FEATURE_SET start/stop device DMA logging.
+ * VFIO_DEVICE_FEATURE_PROBE can be used to detect if the device supports
+ * DMA logging.
+ *
+ * DMA logging allows a device to internally record what DMAs the device is
+ * initiating and report them back to userspace. It is part of the VFIO
+ * migration infrastructure that allows implementing dirty page tracking
+ * during the pre copy phase of live migration. Only DMA WRITEs are logged,
+ * and this API is not connected to VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE.
+ *
+ * When DMA logging is started a range of IOVAs to monitor is provided and the
+ * device can optimize its logging to cover only the IOVA range given. Each
+ * DMA that the device initiates inside the range will be logged by the device
+ * for later retrieval.
+ *
+ * page_size is an input that hints what tracking granularity the device
+ * should try to achieve. If the device cannot do the hinted page size then
+ * it's the driver choice which page size to pick based on its support.
+ * On output the device will return the page size it selected.
+ *
+ * ranges is a pointer to an array of
+ * struct vfio_device_feature_dma_logging_range.
+ *
+ * The core kernel code guarantees to support by minimum num_ranges that fit
+ * into a single kernel page. User space can try higher values but should give
+ * up if the above can't be achieved as of some driver limitations.
+ *
+ * A single call to start device DMA logging can be issued and a matching stop
+ * should follow at the end. Another start is not allowed in the meantime.
+ */
+struct vfio_device_feature_dma_logging_control {
+ __aligned_u64 page_size;
+ __u32 num_ranges;
+ __u32 __reserved;
+ __aligned_u64 ranges;
+};
+
+struct vfio_device_feature_dma_logging_range {
+ __aligned_u64 iova;
+ __aligned_u64 length;
+};
+
+#define VFIO_DEVICE_FEATURE_DMA_LOGGING_START 6
+
+/*
+ * Upon VFIO_DEVICE_FEATURE_SET stop device DMA logging that was started
+ * by VFIO_DEVICE_FEATURE_DMA_LOGGING_START
+ */
+#define VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP 7
+
+/*
+ * Upon VFIO_DEVICE_FEATURE_GET read back and clear the device DMA log
+ *
+ * Query the device's DMA log for written pages within the given IOVA range.
+ * During querying the log is cleared for the IOVA range.
+ *
+ * bitmap is a pointer to an array of u64s that will hold the output bitmap
+ * with 1 bit reporting a page_size unit of IOVA. The mapping of IOVA to bits
+ * is given by:
+ * bitmap[(addr - iova)/page_size] & (1ULL << (addr % 64))
+ *
+ * The input page_size can be any power of two value and does not have to
+ * match the value given to VFIO_DEVICE_FEATURE_DMA_LOGGING_START. The driver
+ * will format its internal logging to match the reporting page size, possibly
+ * by replicating bits if the internal page size is lower than requested.
+ *
+ * The LOGGING_REPORT will only set bits in the bitmap and never clear or
+ * perform any initialization of the user provided bitmap.
+ *
+ * If any error is returned userspace should assume that the dirty log is
+ * corrupted. Error recovery is to consider all memory dirty and try to
+ * restart the dirty tracking, or to abort/restart the whole migration.
+ *
+ * If DMA logging is not enabled, an error will be returned.
+ *
+ */
+struct vfio_device_feature_dma_logging_report {
+ __aligned_u64 iova;
+ __aligned_u64 length;
+ __aligned_u64 page_size;
+ __aligned_u64 bitmap;
+};
+
+#define VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT 8
+
/* -------- API for Type1 VFIO IOMMU -------- */
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions
2022-10-27 5:46 [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions Mayuresh Chitale
2022-10-27 5:46 ` [PATCH v1 1/3] update-linux-headers: Version 6.1-rc2 Mayuresh Chitale
@ 2022-10-27 5:46 ` Mayuresh Chitale
2022-10-27 23:09 ` Alistair Francis
2022-10-27 5:46 ` [PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions Mayuresh Chitale
2022-10-27 8:24 ` [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions Andrew Jones
3 siblings, 1 reply; 7+ messages in thread
From: Mayuresh Chitale @ 2022-10-27 5:46 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis
Currently the ISA string for a CPU is generated from two different
arrays, one for single letter extensions and another for multi letter
extensions. Add all the single letter extensions to the isa_ext_data
array and use it for generating the ISA string. Also drop 'P' and 'Q'
extensions from the list of single letter extensions as those are not
supported yet.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
target/riscv/cpu.c | 41 +++++++++++++++++++++++------------------
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e6d9c706bb..35320a8547 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -41,8 +41,6 @@
(QEMU_VERSION_MICRO))
#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
-static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
-
struct isa_ext_data {
const char *name;
bool multi_letter;
@@ -71,6 +69,13 @@ struct isa_ext_data {
* extensions by an underscore.
*/
static const struct isa_ext_data isa_edata_arr[] = {
+ ISA_EXT_DATA_ENTRY(i, false, PRIV_VERSION_1_10_0, ext_i),
+ ISA_EXT_DATA_ENTRY(e, false, PRIV_VERSION_1_10_0, ext_e),
+ ISA_EXT_DATA_ENTRY(m, false, PRIV_VERSION_1_10_0, ext_m),
+ ISA_EXT_DATA_ENTRY(a, false, PRIV_VERSION_1_10_0, ext_a),
+ ISA_EXT_DATA_ENTRY(f, false, PRIV_VERSION_1_10_0, ext_f),
+ ISA_EXT_DATA_ENTRY(d, false, PRIV_VERSION_1_10_0, ext_d),
+ ISA_EXT_DATA_ENTRY(c, false, PRIV_VERSION_1_10_0, ext_c),
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
@@ -1182,16 +1187,23 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}
-static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str)
{
char *old = *isa_str;
char *new = *isa_str;
int i;
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_edata_arr[i].multi_letter &&
- isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
- new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+ if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
+ if (isa_edata_arr[i].multi_letter) {
+ if (cpu->cfg.short_isa_string) {
+ continue;
+ }
+ new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+ } else {
+ new = g_strconcat(old, isa_edata_arr[i].name, NULL);
+ }
+
g_free(old);
old = new;
}
@@ -1202,19 +1214,12 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
char *riscv_isa_string(RISCVCPU *cpu)
{
- int i;
- const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
+ const size_t maxlen = sizeof("rv128");
char *isa_str = g_new(char, maxlen);
- char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
- for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
- if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
- *p++ = qemu_tolower(riscv_single_letter_exts[i]);
- }
- }
- *p = '\0';
- if (!cpu->cfg.short_isa_string) {
- riscv_isa_string_ext(cpu, &isa_str, maxlen);
- }
+
+ snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
+ riscv_isa_string_ext(cpu, &isa_str);
+
return isa_str;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions
2022-10-27 5:46 ` [PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions Mayuresh Chitale
@ 2022-10-27 23:09 ` Alistair Francis
0 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-10-27 23:09 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: qemu-devel, qemu-riscv, alistair.francis
On Thu, Oct 27, 2022 at 3:50 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Currently the ISA string for a CPU is generated from two different
> arrays, one for single letter extensions and another for multi letter
> extensions. Add all the single letter extensions to the isa_ext_data
> array and use it for generating the ISA string. Also drop 'P' and 'Q'
> extensions from the list of single letter extensions as those are not
> supported yet.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 41 +++++++++++++++++++++++------------------
> 1 file changed, 23 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e6d9c706bb..35320a8547 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -41,8 +41,6 @@
> (QEMU_VERSION_MICRO))
> #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
>
> -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
> -
> struct isa_ext_data {
> const char *name;
> bool multi_letter;
> @@ -71,6 +69,13 @@ struct isa_ext_data {
> * extensions by an underscore.
> */
> static const struct isa_ext_data isa_edata_arr[] = {
> + ISA_EXT_DATA_ENTRY(i, false, PRIV_VERSION_1_10_0, ext_i),
> + ISA_EXT_DATA_ENTRY(e, false, PRIV_VERSION_1_10_0, ext_e),
> + ISA_EXT_DATA_ENTRY(m, false, PRIV_VERSION_1_10_0, ext_m),
> + ISA_EXT_DATA_ENTRY(a, false, PRIV_VERSION_1_10_0, ext_a),
> + ISA_EXT_DATA_ENTRY(f, false, PRIV_VERSION_1_10_0, ext_f),
> + ISA_EXT_DATA_ENTRY(d, false, PRIV_VERSION_1_10_0, ext_d),
> + ISA_EXT_DATA_ENTRY(c, false, PRIV_VERSION_1_10_0, ext_c),
> ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
> ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
> ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
> @@ -1182,16 +1187,23 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> -static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str)
> {
> char *old = *isa_str;
> char *new = *isa_str;
> int i;
>
> for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> - if (isa_edata_arr[i].multi_letter &&
> - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
> - new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
> + if (isa_edata_arr[i].multi_letter) {
> + if (cpu->cfg.short_isa_string) {
> + continue;
> + }
> + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> + } else {
> + new = g_strconcat(old, isa_edata_arr[i].name, NULL);
> + }
> +
> g_free(old);
> old = new;
> }
> @@ -1202,19 +1214,12 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
>
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> - int i;
> - const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
> + const size_t maxlen = sizeof("rv128");
> char *isa_str = g_new(char, maxlen);
> - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> - for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
> - if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
> - *p++ = qemu_tolower(riscv_single_letter_exts[i]);
> - }
> - }
> - *p = '\0';
> - if (!cpu->cfg.short_isa_string) {
> - riscv_isa_string_ext(cpu, &isa_str, maxlen);
> - }
> +
> + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> + riscv_isa_string_ext(cpu, &isa_str);
> +
> return isa_str;
> }
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions
2022-10-27 5:46 [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions Mayuresh Chitale
2022-10-27 5:46 ` [PATCH v1 1/3] update-linux-headers: Version 6.1-rc2 Mayuresh Chitale
2022-10-27 5:46 ` [PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions Mayuresh Chitale
@ 2022-10-27 5:46 ` Mayuresh Chitale
2022-11-14 3:48 ` Alistair Francis
2022-10-27 8:24 ` [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions Andrew Jones
3 siblings, 1 reply; 7+ messages in thread
From: Mayuresh Chitale @ 2022-10-27 5:46 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis
Set the state of each ISA extension on the vcpu depending on what
is set in the CPU property and what is allowed by KVM for that extension.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
target/riscv/cpu.c | 11 ++++-
target/riscv/kvm.c | 88 ++++++++++++++++++++++++++++++++++------
target/riscv/kvm_riscv.h | 2 +-
3 files changed, 87 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 35320a8547..e52577d59d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1191,10 +1191,19 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str)
{
char *old = *isa_str;
char *new = *isa_str;
- int i;
+ int i, offset;
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
+ offset = isa_edata_arr[i].ext_enable_offset;
+ if (kvm_enabled() && !kvm_riscv_ext_supported(offset)) {
+#ifndef CONFIG_USER_ONLY
+ info_report("disabling %s extension for hart 0x%lx because "
+ "kvm does not support it", isa_edata_arr[i].name,
+ (unsigned long)cpu->env.mhartid);
+#endif
+ continue;
+ }
if (isa_edata_arr[i].multi_letter) {
if (cpu->cfg.short_isa_string) {
continue;
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 30f21453d6..ea0715c9e4 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -42,6 +42,29 @@
#include "migration/migration.h"
#include "sysemu/runstate.h"
+struct isa_ext_info {
+ const char *name;
+ target_ulong misa_bit;
+ int ext_enable_offset;
+};
+
+#define ISA_EXT_DATA_ENTRY(_name, _bit, _prop) \
+ {#_name, _bit, offsetof(struct RISCVCPUConfig, _prop)}
+
+static const struct isa_ext_info isa_info_arr[] = {
+ ISA_EXT_DATA_ENTRY(a, RVA, ext_a),
+ ISA_EXT_DATA_ENTRY(c, RVC, ext_c),
+ ISA_EXT_DATA_ENTRY(d, RVD, ext_d),
+ ISA_EXT_DATA_ENTRY(f, RVF, ext_f),
+ ISA_EXT_DATA_ENTRY(h, RVH, ext_h),
+ ISA_EXT_DATA_ENTRY(i, RVI, ext_i),
+ ISA_EXT_DATA_ENTRY(m, RVM, ext_m),
+ ISA_EXT_DATA_ENTRY(svpbmt, 0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(sstc, 0, ext_sstc),
+ ISA_EXT_DATA_ENTRY(svinval, 0, ext_svinval),
+ ISA_EXT_DATA_ENTRY(zihintpause, 0, ext_zihintpause),
+};
+
static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
uint64_t idx)
{
@@ -394,25 +417,66 @@ void kvm_arch_init_irq_routing(KVMState *s)
{
}
+bool kvm_riscv_ext_supported(int offset)
+{
+ int i;
+
+ for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; ++i) {
+ if (isa_info_arr[i].ext_enable_offset == offset) {
+ return true;
+ }
+ }
+ return false;
+}
+
+static void kvm_riscv_set_isa_ext(CPUState *cs, CPURISCVState *env)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ unsigned long isa_ext_out;
+ bool *ext_state;
+ uint64_t id;
+ int i, ret;
+
+ env->misa_ext = 0;
+ for (i = 0; i < ARRAY_SIZE(isa_info_arr); i++) {
+ ext_state = (void *)&cpu->cfg + isa_info_arr[i].ext_enable_offset;
+ id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, i);
+ ret = kvm_get_one_reg(cs, id, &isa_ext_out);
+ if (ret) {
+ warn_report("Disabling ext %s due to failure.",
+ isa_info_arr[i].name);
+ *ext_state = false;
+ continue;
+ }
+ if (isa_ext_out != (*ext_state)) {
+ isa_ext_out = *ext_state;
+ ret = kvm_set_one_reg(cs, id, &isa_ext_out);
+ if (ret) {
+ warn_report("Could not %s ext %s.",
+ (isa_ext_out ? "enable" : "disable"),
+ isa_info_arr[i].name);
+ *ext_state = !isa_ext_out;
+ }
+ }
+ /*
+ * If the sigle letter extension is supported by KVM then set
+ * the corresponding misa bit for the guest vcpu.
+ */
+ if (isa_info_arr[i].misa_bit && (*ext_state)) {
+ env->misa_ext |= isa_info_arr[i].misa_bit;
+ }
+ }
+}
+
int kvm_arch_init_vcpu(CPUState *cs)
{
- int ret = 0;
- target_ulong isa;
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- uint64_t id;
qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
- id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
- KVM_REG_RISCV_CONFIG_REG(isa));
- ret = kvm_get_one_reg(cs, id, &isa);
- if (ret) {
- return ret;
- }
- env->misa_ext = isa;
-
- return ret;
+ kvm_riscv_set_isa_ext(cs, env);
+ return 0;
}
int kvm_arch_msi_data_to_gsi(uint32_t data)
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index ed281bdce0..bdcccc0da4 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -21,5 +21,5 @@
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
-
+bool kvm_riscv_ext_supported(int offset);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions
2022-10-27 5:46 ` [PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions Mayuresh Chitale
@ 2022-11-14 3:48 ` Alistair Francis
0 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-11-14 3:48 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: qemu-devel, qemu-riscv, alistair.francis
On Thu, Oct 27, 2022 at 3:53 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Set the state of each ISA extension on the vcpu depending on what
> is set in the CPU property and what is allowed by KVM for that extension.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 11 ++++-
> target/riscv/kvm.c | 88 ++++++++++++++++++++++++++++++++++------
> target/riscv/kvm_riscv.h | 2 +-
> 3 files changed, 87 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 35320a8547..e52577d59d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1191,10 +1191,19 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str)
> {
> char *old = *isa_str;
> char *new = *isa_str;
> - int i;
> + int i, offset;
>
> for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
> + offset = isa_edata_arr[i].ext_enable_offset;
> + if (kvm_enabled() && !kvm_riscv_ext_supported(offset)) {
> +#ifndef CONFIG_USER_ONLY
> + info_report("disabling %s extension for hart 0x%lx because "
> + "kvm does not support it", isa_edata_arr[i].name,
> + (unsigned long)cpu->env.mhartid);
> +#endif
> + continue;
> + }
> if (isa_edata_arr[i].multi_letter) {
> if (cpu->cfg.short_isa_string) {
> continue;
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 30f21453d6..ea0715c9e4 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -42,6 +42,29 @@
> #include "migration/migration.h"
> #include "sysemu/runstate.h"
>
> +struct isa_ext_info {
> + const char *name;
> + target_ulong misa_bit;
> + int ext_enable_offset;
> +};
> +
> +#define ISA_EXT_DATA_ENTRY(_name, _bit, _prop) \
> + {#_name, _bit, offsetof(struct RISCVCPUConfig, _prop)}
> +
> +static const struct isa_ext_info isa_info_arr[] = {
> + ISA_EXT_DATA_ENTRY(a, RVA, ext_a),
> + ISA_EXT_DATA_ENTRY(c, RVC, ext_c),
> + ISA_EXT_DATA_ENTRY(d, RVD, ext_d),
> + ISA_EXT_DATA_ENTRY(f, RVF, ext_f),
> + ISA_EXT_DATA_ENTRY(h, RVH, ext_h),
> + ISA_EXT_DATA_ENTRY(i, RVI, ext_i),
> + ISA_EXT_DATA_ENTRY(m, RVM, ext_m),
> + ISA_EXT_DATA_ENTRY(svpbmt, 0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(sstc, 0, ext_sstc),
> + ISA_EXT_DATA_ENTRY(svinval, 0, ext_svinval),
> + ISA_EXT_DATA_ENTRY(zihintpause, 0, ext_zihintpause),
> +};
> +
> static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
> uint64_t idx)
> {
> @@ -394,25 +417,66 @@ void kvm_arch_init_irq_routing(KVMState *s)
> {
> }
>
> +bool kvm_riscv_ext_supported(int offset)
> +{
> + int i;
> +
> + for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; ++i) {
> + if (isa_info_arr[i].ext_enable_offset == offset) {
> + return true;
> + }
> + }
> + return false;
> +}
> +
> +static void kvm_riscv_set_isa_ext(CPUState *cs, CPURISCVState *env)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + unsigned long isa_ext_out;
> + bool *ext_state;
> + uint64_t id;
> + int i, ret;
> +
> + env->misa_ext = 0;
> + for (i = 0; i < ARRAY_SIZE(isa_info_arr); i++) {
> + ext_state = (void *)&cpu->cfg + isa_info_arr[i].ext_enable_offset;
> + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, i);
> + ret = kvm_get_one_reg(cs, id, &isa_ext_out);
> + if (ret) {
> + warn_report("Disabling ext %s due to failure.",
> + isa_info_arr[i].name);
> + *ext_state = false;
> + continue;
> + }
> + if (isa_ext_out != (*ext_state)) {
> + isa_ext_out = *ext_state;
> + ret = kvm_set_one_reg(cs, id, &isa_ext_out);
> + if (ret) {
> + warn_report("Could not %s ext %s.",
> + (isa_ext_out ? "enable" : "disable"),
> + isa_info_arr[i].name);
> + *ext_state = !isa_ext_out;
> + }
> + }
> + /*
> + * If the sigle letter extension is supported by KVM then set
> + * the corresponding misa bit for the guest vcpu.
> + */
> + if (isa_info_arr[i].misa_bit && (*ext_state)) {
> + env->misa_ext |= isa_info_arr[i].misa_bit;
> + }
> + }
> +}
> +
> int kvm_arch_init_vcpu(CPUState *cs)
> {
> - int ret = 0;
> - target_ulong isa;
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - uint64_t id;
>
> qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
>
> - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
> - KVM_REG_RISCV_CONFIG_REG(isa));
> - ret = kvm_get_one_reg(cs, id, &isa);
> - if (ret) {
> - return ret;
> - }
> - env->misa_ext = isa;
> -
> - return ret;
> + kvm_riscv_set_isa_ext(cs, env);
> + return 0;
> }
>
> int kvm_arch_msi_data_to_gsi(uint32_t data)
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index ed281bdce0..bdcccc0da4 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -21,5 +21,5 @@
>
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> -
> +bool kvm_riscv_ext_supported(int offset);
> #endif
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions
2022-10-27 5:46 [PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions Mayuresh Chitale
` (2 preceding siblings ...)
2022-10-27 5:46 ` [PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions Mayuresh Chitale
@ 2022-10-27 8:24 ` Andrew Jones
3 siblings, 0 replies; 7+ messages in thread
From: Andrew Jones @ 2022-10-27 8:24 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: qemu-devel, qemu-riscv, alistair.francis
On Thu, Oct 27, 2022 at 7:52 AM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Currently the single and multi letter ISA extensions exposed to the guest
> vcpu don't confirm to the KVM policies. This patchset updates the kvm headers
> and applies policies set in KVM to the extensions exposed to the guest.
>
> Mayuresh Chitale (3):
> update-linux-headers: Version 6.1-rc2
> target/riscv: Extend isa_ext_data for single letter extensions
> target/riscv: kvm: Support selecting VCPU extensions
>
I already reviewed this internally and it hasn't changed, so
for the series
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 7+ messages in thread