From: Zev Weiss <zweiss@equinix.com>
To: AKASH G J <akashgj91@gmail.com>
Cc: "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>
Subject: Re: RISC-V Support in OpenBMC
Date: Fri, 28 Oct 2022 11:47:32 +0000 [thread overview]
Message-ID: <20221028114732.GC18848@packtop> (raw)
In-Reply-To: <CAE33tLG4oOjTmNJ=a0jNEEdTj_501offkYUFcEVwk6rAnZYKSw@mail.gmail.com>
On Fri, Oct 28, 2022 at 07:00:00AM PDT, AKASH G J wrote:
>Hi Team,
>
>Whether OpenBMC supports BMC controller with RISC-V architecture? If so,
>how we can generate BMC firmware image for the BMC controller with RISC-V
>architecture.
>
Currently I believe the only BMC SOCs supported in mainline OpenBMC are
the Aspeed AST2x00, Nuvoton NPCM, and HP GXP chips, all of which are ARM
based.
A project with OpenBMC running on a PowerPC-based BMC was also announced
recently (https://codeconstruct.com.au/docs/dcscm-openbmc/), though I
don't think any of that work has made its way upstream so far.
I don't know of any RISC-V based efforts though.
>Are there any BMC SoC available in market with RISC-V architecture?
>
Not that I've heard of at this point.
Zev
prev parent reply other threads:[~2022-10-28 13:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAE33tLG4oOjTmNJ=a0jNEEdTj_501offkYUFcEVwk6rAnZYKSw@mail.gmail.com>
2022-10-28 11:42 ` RISC-V Support in OpenBMC Patrick Williams
2022-10-28 11:47 ` Zev Weiss [this message]
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