Re: RISC-V Support in OpenBMC

Re: RISC-V Support in OpenBMC

[Patrick Williams]

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On Fri, Oct 28, 2022 at 07:30:00PM +0530, AKASH G J wrote:
> Whether OpenBMC supports BMC controller with RISC-V architecture? If so,
> how we can generate BMC firmware image for the BMC controller with RISC-V
> architecture.

There is nothing to preclude a RISC-V based BMC being contributed and
running OpenBMC.  Yocto already supports RISC-V, so it should not be
difficult other than getting kernel support for whichever SOC you end up
with.

I am not aware of any RISC-V BMC chips at this time.

-- 
Patrick Williams

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Re: RISC-V Support in OpenBMC

[Zev Weiss]

On Fri, Oct 28, 2022 at 07:00:00AM PDT, AKASH G J wrote:
>Hi Team,
>
>Whether OpenBMC supports BMC controller with RISC-V architecture? If so,
>how we can generate BMC firmware image for the BMC controller with RISC-V
>architecture.
>

Currently I believe the only BMC SOCs supported in mainline OpenBMC are
the Aspeed AST2x00, Nuvoton NPCM, and HP GXP chips, all of which are ARM
based.

A project with OpenBMC running on a PowerPC-based BMC was also announced
recently (https://codeconstruct.com.au/docs/dcscm-openbmc/), though I
don't think any of that work has made its way upstream so far.

I don't know of any RISC-V based efforts though.

>Are there any BMC SoC available in market with RISC-V architecture?
>

Not that I've heard of at this point.


Zev