From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Mauro Lima <mauro.lima@eclypsium.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Mark Brown <broonie@kernel.org>, Sasha Levin <sashal@kernel.org>,
tudor.ambarus@microchip.com, pratyush@kernel.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
linux-mtd@lists.infradead.org
Subject: [PATCH AUTOSEL 5.4 05/12] spi: intel: Fix the offset to get the 64K erase opcode
Date: Sun, 6 Nov 2022 12:06:29 -0500 [thread overview]
Message-ID: <20221106170637.1580802-5-sashal@kernel.org> (raw)
In-Reply-To: <20221106170637.1580802-1-sashal@kernel.org>
From: Mauro Lima <mauro.lima@eclypsium.com>
[ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ]
According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.
Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/mtd/spi-nor/intel-spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index 43e55a2e9b27..21b98c82e196 100644
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -113,7 +113,7 @@
#define ERASE_OPCODE_SHIFT 8
#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
#define ERASE_64K_OPCODE_SHIFT 16
-#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
+#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
#define INTEL_SPI_TIMEOUT 5000 /* ms */
#define INTEL_SPI_FIFO_SZ 64
--
2.35.1
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WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Mauro Lima <mauro.lima@eclypsium.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Mark Brown <broonie@kernel.org>, Sasha Levin <sashal@kernel.org>,
tudor.ambarus@microchip.com, pratyush@kernel.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
linux-mtd@lists.infradead.org
Subject: [PATCH AUTOSEL 5.4 05/12] spi: intel: Fix the offset to get the 64K erase opcode
Date: Sun, 6 Nov 2022 12:06:29 -0500 [thread overview]
Message-ID: <20221106170637.1580802-5-sashal@kernel.org> (raw)
In-Reply-To: <20221106170637.1580802-1-sashal@kernel.org>
From: Mauro Lima <mauro.lima@eclypsium.com>
[ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ]
According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.
Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/mtd/spi-nor/intel-spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index 43e55a2e9b27..21b98c82e196 100644
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -113,7 +113,7 @@
#define ERASE_OPCODE_SHIFT 8
#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
#define ERASE_64K_OPCODE_SHIFT 16
-#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
+#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
#define INTEL_SPI_TIMEOUT 5000 /* ms */
#define INTEL_SPI_FIFO_SZ 64
--
2.35.1
next prev parent reply other threads:[~2022-11-06 17:07 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-06 17:06 [PATCH AUTOSEL 5.4 01/12] ASoC: wm5102: Revert "ASoC: wm5102: Fix PM disable depth imbalance in wm5102_probe" Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 02/12] ASoC: wm5110: Revert "ASoC: wm5110: Fix PM disable depth imbalance in wm5110_probe" Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 03/12] ASoC: wm8997: Revert "ASoC: wm8997: Fix PM disable depth imbalance in wm8997_probe" Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 04/12] ASoC: wm8962: Add an event handler for TEMP_HP and TEMP_SPK Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` Sasha Levin [this message]
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 05/12] spi: intel: Fix the offset to get the 64K erase opcode Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 06/12] ASoC: codecs: jz4725b: add missed Line In power control bit Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 07/12] ASoC: codecs: jz4725b: fix reported volume for Master ctl Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 08/12] ASoC: codecs: jz4725b: use right control for Capture Volume Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 09/12] ASoC: codecs: jz4725b: fix capture selector naming Sasha Levin
2022-11-06 17:06 ` Sasha Levin
2022-11-06 17:44 ` Siarhei Volkau
2022-11-06 17:44 ` Siarhei Volkau
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 10/12] selftests/futex: fix build for clang Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 11/12] selftests/intel_pstate: fix build for ARCH=x86_64 Sasha Levin
2022-11-06 17:06 ` [PATCH AUTOSEL 5.4 12/12] rtc: cmos: fix build on non-ACPI platforms Sasha Levin
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