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From: Matt Ranostay <mranostay@ti.com>
To: <vigneshr@ti.com>, <lpieralisi@kernel.org>, <robh@kernel.org>,
	<kw@linux.com>, <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Matt Ranostay <mranostay@ti.com>, Achal Verma <a-verma1@ti.com>
Subject: [PATCH v6 5/5] PCI: j721e: add j784s4 PCIe configuration
Date: Tue, 15 Nov 2022 07:03:35 -0800	[thread overview]
Message-ID: <20221115150335.501502-6-mranostay@ti.com> (raw)
In-Reply-To: <20221115150335.501502-1-mranostay@ti.com>

Add PCIe configuration for j784s4 platform which has 4x lane support.

Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index dab3db9be6d8..c484d658c18a 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
 	.max_lanes = 1,
 };
 
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+	.mode = PCI_MODE_RC,
+	.quirk_retrain_flag = true,
+	.is_intc_v1 = true,
+	.byte_access_allowed = false,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+	.mode = PCI_MODE_EP,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
 static const struct of_device_id of_j721e_pcie_match[] = {
 	{
 		.compatible = "ti,j721e-pcie-host",
@@ -355,6 +370,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
 		.compatible = "ti,am64-pcie-ep",
 		.data = &am64_pcie_ep_data,
 	},
+	{
+		.compatible = "ti,j784s4-pcie-host",
+		.data = &j784s4_pcie_rc_data,
+	},
+	{
+		.compatible = "ti,j784s4-pcie-ep",
+		.data = &j784s4_pcie_ep_data,
+	},
 	{},
 };
 
-- 
2.38.GIT


WARNING: multiple messages have this Message-ID (diff)
From: Matt Ranostay <mranostay@ti.com>
To: <vigneshr@ti.com>, <lpieralisi@kernel.org>, <robh@kernel.org>,
	<kw@linux.com>, <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Matt Ranostay <mranostay@ti.com>, Achal Verma <a-verma1@ti.com>
Subject: [PATCH v6 5/5] PCI: j721e: add j784s4 PCIe configuration
Date: Tue, 15 Nov 2022 07:03:35 -0800	[thread overview]
Message-ID: <20221115150335.501502-6-mranostay@ti.com> (raw)
In-Reply-To: <20221115150335.501502-1-mranostay@ti.com>

Add PCIe configuration for j784s4 platform which has 4x lane support.

Tested-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index dab3db9be6d8..c484d658c18a 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
 	.max_lanes = 1,
 };
 
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+	.mode = PCI_MODE_RC,
+	.quirk_retrain_flag = true,
+	.is_intc_v1 = true,
+	.byte_access_allowed = false,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+	.mode = PCI_MODE_EP,
+	.linkdown_irq_regfield = LINK_DOWN,
+	.max_lanes = 4,
+};
+
 static const struct of_device_id of_j721e_pcie_match[] = {
 	{
 		.compatible = "ti,j721e-pcie-host",
@@ -355,6 +370,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
 		.compatible = "ti,am64-pcie-ep",
 		.data = &am64_pcie_ep_data,
 	},
+	{
+		.compatible = "ti,j784s4-pcie-host",
+		.data = &j784s4_pcie_rc_data,
+	},
+	{
+		.compatible = "ti,j784s4-pcie-ep",
+		.data = &j784s4_pcie_ep_data,
+	},
 	{},
 };
 
-- 
2.38.GIT


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  parent reply	other threads:[~2022-11-15 15:09 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-15 15:03 [PATCH v6 0/5] PCI: add 4x lane support for pci-j721e controllers Matt Ranostay
2022-11-15 15:03 ` Matt Ranostay
2022-11-15 15:03 ` [PATCH v6 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Matt Ranostay
2022-11-15 15:03   ` Matt Ranostay
2022-11-23 16:04   ` Krzysztof Kozlowski
2022-11-23 16:04     ` Krzysztof Kozlowski
2022-11-24  7:58     ` Matt Ranostay
2022-11-24  7:58       ` Matt Ranostay
2022-11-24  9:26       ` Krzysztof Kozlowski
2022-11-24  9:26         ` Krzysztof Kozlowski
2022-11-15 15:03 ` [PATCH v6 2/5] PCI: j721e: Add per platform maximum lane settings Matt Ranostay
2022-11-15 15:03   ` Matt Ranostay
2022-11-15 15:03 ` [PATCH v6 3/5] PCI: j721e: Add PCIe 4x lane selection support Matt Ranostay
2022-11-15 15:03   ` Matt Ranostay
2022-11-15 15:03 ` [PATCH v6 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Matt Ranostay
2022-11-15 15:03   ` Matt Ranostay
2022-11-23 16:04   ` Krzysztof Kozlowski
2022-11-23 16:04     ` Krzysztof Kozlowski
2022-11-15 15:03 ` Matt Ranostay [this message]
2022-11-15 15:03   ` [PATCH v6 5/5] PCI: j721e: add j784s4 PCIe configuration Matt Ranostay
2022-11-21 21:09   ` kernel test robot
2022-11-15 15:37 ` [PATCH v6 0/5] PCI: add 4x lane support for pci-j721e controllers Bjorn Helgaas
2022-11-15 15:37   ` Bjorn Helgaas
2022-11-23  5:51   ` Matt Ranostay
2022-11-23  5:51     ` Matt Ranostay

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