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From: Moudy Ho <moudy.ho@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Roy-CW.Yeh <roy-cw.yeh@mediatek.com>,
	Moudy Ho <moudy.ho@mediatek.com>
Subject: [PATCH v4 7/8] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1
Date: Wed, 7 Dec 2022 17:49:20 +0800	[thread overview]
Message-ID: <20221207094921.15450-8-moudy.ho@mediatek.com> (raw)
In-Reply-To: <20221207094921.15450-1-moudy.ho@mediatek.com>

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add mtk_mutex_set_mod support to set MOD1

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 33 +++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c1a33d52038e..a2be15a5c93a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -23,6 +23,7 @@
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg) + 0x20 * (n) + 0x4)
 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
 
@@ -740,7 +741,7 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
 	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
 						 mutex[mutex->id]);
 	unsigned int reg;
-	unsigned int offset;
+	u32 reg_offset, id_offset = 0;
 
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
@@ -750,16 +751,34 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
 		return -EINVAL;
 	}
 
-	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
-				    mutex->id);
-	reg = readl_relaxed(mtx->regs + offset);
+	/*
+	 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
+	 * are present, hence requiring multiple 32-bits registers.
+	 *
+	 * The mutex_table_mod fully represents that by defining the number of
+	 * the mod sequentially, later used as a bit number, which can be more
+	 * than 0..31.
+	 *
+	 * In order to retain compatibility with older SoCs, we perform R/W on
+	 * the single 32 bits registers, but this requires us to translate the
+	 * mutex ID bit accordingly.
+	 */
+	if (mtx->data->mutex_table_mod[idx] < 32) {
+		reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
+						mutex->id);
+	} else {
+		reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
+						 mutex->id);
+		id_offset = 32;
+	}
 
+	reg = readl_relaxed(mtx->regs + reg_offset);
 	if (clear)
-		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
+		reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset);
 	else
-		reg |= BIT(mtx->data->mutex_table_mod[idx]);
+		reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset);
 
-	writel_relaxed(reg, mtx->regs + offset);
+	writel_relaxed(reg, mtx->regs + reg_offset);
 
 	return 0;
 }
-- 
2.18.0



WARNING: multiple messages have this Message-ID (diff)
From: Moudy Ho <moudy.ho@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Roy-CW.Yeh <roy-cw.yeh@mediatek.com>,
	Moudy Ho <moudy.ho@mediatek.com>
Subject: [PATCH v4 7/8] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1
Date: Wed, 7 Dec 2022 17:49:20 +0800	[thread overview]
Message-ID: <20221207094921.15450-8-moudy.ho@mediatek.com> (raw)
In-Reply-To: <20221207094921.15450-1-moudy.ho@mediatek.com>

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add mtk_mutex_set_mod support to set MOD1

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 33 +++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c1a33d52038e..a2be15a5c93a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -23,6 +23,7 @@
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg) + 0x20 * (n) + 0x4)
 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
 
@@ -740,7 +741,7 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
 	struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
 						 mutex[mutex->id]);
 	unsigned int reg;
-	unsigned int offset;
+	u32 reg_offset, id_offset = 0;
 
 	WARN_ON(&mtx->mutex[mutex->id] != mutex);
 
@@ -750,16 +751,34 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
 		return -EINVAL;
 	}
 
-	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
-				    mutex->id);
-	reg = readl_relaxed(mtx->regs + offset);
+	/*
+	 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
+	 * are present, hence requiring multiple 32-bits registers.
+	 *
+	 * The mutex_table_mod fully represents that by defining the number of
+	 * the mod sequentially, later used as a bit number, which can be more
+	 * than 0..31.
+	 *
+	 * In order to retain compatibility with older SoCs, we perform R/W on
+	 * the single 32 bits registers, but this requires us to translate the
+	 * mutex ID bit accordingly.
+	 */
+	if (mtx->data->mutex_table_mod[idx] < 32) {
+		reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
+						mutex->id);
+	} else {
+		reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
+						 mutex->id);
+		id_offset = 32;
+	}
 
+	reg = readl_relaxed(mtx->regs + reg_offset);
 	if (clear)
-		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
+		reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset);
 	else
-		reg |= BIT(mtx->data->mutex_table_mod[idx]);
+		reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset);
 
-	writel_relaxed(reg, mtx->regs + offset);
+	writel_relaxed(reg, mtx->regs + reg_offset);
 
 	return 0;
 }
-- 
2.18.0


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  parent reply	other threads:[~2022-12-07  9:53 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-07  9:49 [PATCH v4 0/8] add support MDP3 on MT8195 platform Moudy Ho
2022-12-07  9:49 ` Moudy Ho
2022-12-07  9:49 ` [PATCH v4 1/8] dt-bindings: arm: mediatek: mmsys: Add support for MT8195 VPPSYS Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-07 10:15   ` AngeloGioacchino Del Regno
2022-12-07 10:15     ` AngeloGioacchino Del Regno
2022-12-19 13:44   ` Rob Herring
2022-12-19 13:44     ` Rob Herring
2022-12-19 15:17     ` Matthias Brugger
2022-12-19 15:17       ` Matthias Brugger
2022-12-19 15:31       ` Krzysztof Kozlowski
2022-12-19 15:31         ` Krzysztof Kozlowski
2022-12-07  9:49 ` [PATCH v4 2/8] dt-bindings: soc: mediatek: " Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-07  9:49 ` [PATCH v4 3/8] arm64: dts: mediatek: mt8195: add MMSYS configuration for VPPSYS Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-07 10:15   ` AngeloGioacchino Del Regno
2022-12-07 10:15     ` AngeloGioacchino Del Regno
2022-12-07  9:49 ` [PATCH v4 4/8] arm64: dts: mediatek: mt8195: add MUTEX " Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-07  9:49 ` [PATCH v4 5/8] soc: mediatek: mmsys: add support for MT8195 VPPSYS Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-07  9:49 ` [PATCH v4 6/8] soc: mediatek: mmsys: add config api for RSZ switching and DCM Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-07  9:49 ` Moudy Ho [this message]
2022-12-07  9:49   ` [PATCH v4 7/8] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1 Moudy Ho
2022-12-07  9:49 ` [PATCH v4 8/8] soc: mediatek: mutex: support MT8195 VPPSYS Moudy Ho
2022-12-07  9:49   ` Moudy Ho
2022-12-16 12:33 ` [PATCH v4 0/8] add support MDP3 on MT8195 platform Matthias Brugger
2022-12-16 12:33   ` Matthias Brugger
2022-12-19 15:17   ` Matthias Brugger
2022-12-19 15:17     ` Matthias Brugger
2022-12-20  2:14     ` Moudy Ho (何宗原)
2022-12-20  2:14       ` Moudy Ho (何宗原)
2022-12-20  3:40       ` Moudy Ho (何宗原)
2022-12-20  3:40         ` Moudy Ho (何宗原)
2022-12-20 14:55         ` Matthias Brugger
2022-12-20 14:55           ` Matthias Brugger

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