From: Rob Herring <robh@kernel.org>
To: Marek Vasut <marex@denx.de>
Cc: devicetree@vger.kernel.org,
Alexander Stein <alexander.stein@ew.tq-group.com>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Lucas Stach <l.stach@pengutronix.de>,
Richard Zhu <hongxing.zhu@nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
linux-arm-kernel@lists.infradead.org,
NXP Linux Team <linux-imx@nxp.com>
Subject: Re: [PATCH v6 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations
Date: Wed, 14 Dec 2022 09:05:26 -0600 [thread overview]
Message-ID: <20221214150526.GA1052624-robh@kernel.org> (raw)
In-Reply-To: <20221211024859.672076-1-marex@denx.de>
On Sun, Dec 11, 2022 at 03:48:57AM +0100, Marek Vasut wrote:
> The i.MX SoCs have various clock configurations routed into the PCIe IP,
> the list of clock is below. Document all those configurations in the DT
> binding document.
>
> All SoCs: pcie, pcie_bus
> 6QDL, 7D: + pcie_phy
> 6SX: + pcie_phy pcie_inbound_axi
> 8MQ: + pcie_phy pcie_aux
> 8MM, 8MP: + pcie_aux
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: devicetree@vger.kernel.org
> ---
> V2: - Add AB from Alex
> V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles
> - Flatten the if-else structure
> - The validation no longer works and introduces errors like these:
> arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected
> V4: - Reinstate minItems: for clock-names in main section, turn the
> last two clock-names items into enums to cover all IP variants.
> - Add another allOf entry for mx6q/mx6qp/mx7d clock-names list.
> - Adjust clock maxItems in the allOf section.
> V5: - No change
> V6: - Add RB from Rob
This should have also gone to PCI maintainers and list so they could
pick it up. However, I'll apply the series.
Rob
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Marek Vasut <marex@denx.de>
Cc: devicetree@vger.kernel.org,
Alexander Stein <alexander.stein@ew.tq-group.com>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Lucas Stach <l.stach@pengutronix.de>,
Richard Zhu <hongxing.zhu@nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
linux-arm-kernel@lists.infradead.org,
NXP Linux Team <linux-imx@nxp.com>
Subject: Re: [PATCH v6 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations
Date: Wed, 14 Dec 2022 09:05:26 -0600 [thread overview]
Message-ID: <20221214150526.GA1052624-robh@kernel.org> (raw)
In-Reply-To: <20221211024859.672076-1-marex@denx.de>
On Sun, Dec 11, 2022 at 03:48:57AM +0100, Marek Vasut wrote:
> The i.MX SoCs have various clock configurations routed into the PCIe IP,
> the list of clock is below. Document all those configurations in the DT
> binding document.
>
> All SoCs: pcie, pcie_bus
> 6QDL, 7D: + pcie_phy
> 6SX: + pcie_phy pcie_inbound_axi
> 8MQ: + pcie_phy pcie_aux
> 8MM, 8MP: + pcie_aux
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: devicetree@vger.kernel.org
> ---
> V2: - Add AB from Alex
> V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles
> - Flatten the if-else structure
> - The validation no longer works and introduces errors like these:
> arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected
> V4: - Reinstate minItems: for clock-names in main section, turn the
> last two clock-names items into enums to cover all IP variants.
> - Add another allOf entry for mx6q/mx6qp/mx7d clock-names list.
> - Adjust clock maxItems in the allOf section.
> V5: - No change
> V6: - Add RB from Rob
This should have also gone to PCI maintainers and list so they could
pick it up. However, I'll apply the series.
Rob
next prev parent reply other threads:[~2022-12-14 15:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-11 2:48 [PATCH v6 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations Marek Vasut
2022-12-11 2:48 ` Marek Vasut
2022-12-11 2:48 ` [PATCH v6 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations Marek Vasut
2022-12-11 2:48 ` Marek Vasut
2022-12-11 2:48 ` [PATCH v6 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms Marek Vasut
2022-12-11 2:48 ` Marek Vasut
2022-12-14 15:05 ` Rob Herring [this message]
2022-12-14 15:05 ` [PATCH v6 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations Rob Herring
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