From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: tsimpson@quicinc.com, richard.henderson@linaro.org,
philmd@linaro.org, peter.maydell@linaro.org, bcain@quicinc.com,
quic_mathbern@quicinc.com, stefanha@redhat.com,
Paolo Montesel <babush@rev.ng>,
Alessandro Di Federico <ale@rev.ng>
Subject: [PULL 14/21] target/hexagon: make slot number an unsigned
Date: Fri, 16 Dec 2022 12:48:38 -0800 [thread overview]
Message-ID: <20221216204845.19290-15-tsimpson@quicinc.com> (raw)
In-Reply-To: <20221216204845.19290-1-tsimpson@quicinc.com>
From: Paolo Montesel <babush@rev.ng>
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Paolo Montesel <babush@rev.ng>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20220923173831.227551-4-anjo@rev.ng>
---
target/hexagon/macros.h | 2 +-
target/hexagon/genptr.c | 24 +++++++++++++-----------
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 903503540e..1a31542010 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -202,7 +202,7 @@
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
#ifdef QEMU_GENERATE
-static inline void gen_pred_cancel(TCGv pred, int slot_num)
+static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
{
TCGv slot_mask = tcg_temp_new();
TCGv tmp = tcg_temp_new();
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index a4a79c8454..4cd2a2aeb9 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -30,7 +30,8 @@
#include "gen_tcg.h"
#include "gen_tcg_hvx.h"
-static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
+static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
+ uint32_t slot)
{
TCGv zero = tcg_constant_tl(0);
TCGv slot_mask = tcg_temp_new();
@@ -62,7 +63,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
}
}
-static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
+static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
+ uint32_t slot)
{
TCGv val32 = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
@@ -394,54 +396,54 @@ static inline void gen_store_conditional8(DisasContext *ctx,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
+static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
}
-static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot)
+static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 1, slot);
}
-static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int slot)
+static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store1(cpu_env, vaddr, tmp, slot);
}
-static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot)
+static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 2, slot);
}
-static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int slot)
+static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store2(cpu_env, vaddr, tmp, slot);
}
-static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot)
+static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 4, slot);
}
-static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int slot)
+static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store4(cpu_env, vaddr, tmp, slot);
}
-static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, int slot)
+static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
tcg_gen_mov_i64(hex_store_val64[slot], src);
}
-static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, int slot)
+static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot)
{
TCGv_i64 tmp = tcg_constant_i64(src);
gen_store8(cpu_env, vaddr, tmp, slot);
--
2.17.1
next prev parent reply other threads:[~2022-12-16 20:52 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-16 20:48 [PULL 00/21] Hexagon update: bug fixes, performance, idef-parser Taylor Simpson
2022-12-16 20:48 ` [PULL 01/21] Hexagon (target/hexagon) Add pkt and insn to DisasContext Taylor Simpson
2022-12-16 20:48 ` [PULL 02/21] Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur Taylor Simpson
2022-12-16 20:48 ` [PULL 03/21] Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat Taylor Simpson
2022-12-16 20:48 ` [PULL 04/21] Hexagon (target/hexagon) Only use branch_taken when packet has multi cof Taylor Simpson
2022-12-16 20:48 ` [PULL 05/21] Hexagon (target/hexagon) Remove PC from the runtime state Taylor Simpson
2022-12-16 20:48 ` [PULL 06/21] Hexagon (target/hexagon) Remove next_PC from " Taylor Simpson
2022-12-16 20:48 ` [PULL 07/21] Hexagon (target/hexagon) Add overrides for direct call instructions Taylor Simpson
2022-12-16 20:48 ` [PULL 08/21] Hexagon (target/hexagon) Add overrides for compound compare and jump Taylor Simpson
2022-12-16 20:48 ` [PULL 09/21] Hexagon (target/hexagon) Add overrides for various forms of jump Taylor Simpson
2022-12-16 20:48 ` [PULL 10/21] Hexagon (target/hexagon) Use direct block chaining for direct jump/branch Taylor Simpson
2022-12-16 20:48 ` [PULL 11/21] Hexagon (target/hexagon) Use direct block chaining for tight loops Taylor Simpson
2022-12-16 20:48 ` [PULL 12/21] target/hexagon: update MAINTAINERS for idef-parser Taylor Simpson
2022-12-16 20:48 ` [PULL 13/21] target/hexagon: import README " Taylor Simpson
2022-12-16 20:48 ` Taylor Simpson [this message]
2022-12-16 20:48 ` [PULL 15/21] target/hexagon: make helper functions non-static Taylor Simpson
2022-12-16 20:48 ` [PULL 16/21] target/hexagon: introduce new helper functions Taylor Simpson
2022-12-16 20:48 ` [PULL 17/21] target/hexagon: prepare input for the idef-parser Taylor Simpson
2022-12-29 10:41 ` Thomas Huth
2022-12-31 14:00 ` Alessandro Di Federico via
2022-12-16 20:48 ` [PULL 18/21] target/hexagon: import lexer for idef-parser Taylor Simpson
2022-12-16 20:48 ` [PULL 19/21] target/hexagon: import parser " Taylor Simpson
2023-06-23 12:50 ` Peter Maydell
2023-06-26 9:54 ` Anton Johansson via
2022-12-16 20:48 ` [PULL 20/21] target/hexagon: call idef-parser functions Taylor Simpson
2022-12-16 20:48 ` [PULL 21/21] target/hexagon: import additional tests Taylor Simpson
2022-12-17 21:21 ` [PULL 00/21] Hexagon update: bug fixes, performance, idef-parser Peter Maydell
2022-12-18 9:33 ` Anton Johansson via
2022-12-18 13:52 ` Peter Maydell
2022-12-18 15:34 ` Anton Johansson via
2022-12-18 16:53 ` Richard Henderson
2022-12-18 17:01 ` Peter Maydell
2022-12-19 11:18 ` Philippe Mathieu-Daudé
2022-12-19 10:28 ` Peter Maydell
2022-12-19 18:54 ` Taylor Simpson
2022-12-20 12:49 ` Alessandro Di Federico via
2022-12-19 23:19 ` Philippe Mathieu-Daudé
2022-12-20 7:30 ` Philippe Mathieu-Daudé
2022-12-20 12:51 ` Alessandro Di Federico via
2022-12-20 14:19 ` Philippe Mathieu-Daudé
2022-12-20 18:13 ` Taylor Simpson
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