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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Bin Meng" <bmeng@tinylab.org>
Subject: [PATCH v5 03/11] hw/riscv/sifive_u: use 'fdt' from MachineState
Date: Mon,  2 Jan 2023 08:52:33 -0300	[thread overview]
Message-ID: <20230102115241.25733-4-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com>

The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.

Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
 hw/riscv/sifive_u.c         | 15 ++++++---------
 include/hw/riscv/sifive_u.h |  3 ---
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a58ddb36ac..ddceb750ea 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
 {
     MachineState *ms = MACHINE(qdev_get_machine());
     void *fdt;
-    int cpu;
+    int cpu, fdt_size;
     uint32_t *cells;
     char *nodename;
     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
@@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     };
 
     if (ms->dtb) {
-        fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
+        fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
         if (!fdt) {
             error_report("load_device_tree() failed");
             exit(1);
         }
         goto update_bootargs;
     } else {
-        fdt = s->fdt = create_device_tree(&s->fdt_size);
+        fdt = ms->fdt = create_device_tree(&fdt_size);
         if (!fdt) {
             error_report("create_device_tree() failed");
             exit(1);
@@ -612,9 +612,9 @@ static void sifive_u_machine_init(MachineState *machine)
             hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                            machine->ram_size, kernel_entry,
                                            &start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen",
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
                                   "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
                                   end);
         }
     } else {
@@ -627,14 +627,11 @@ static void sifive_u_machine_init(MachineState *machine)
 
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
-                                   machine->ram_size, s->fdt);
+                                   machine->ram_size, machine->fdt);
     if (!riscv_is_32bit(&s->soc.u_cpus)) {
         start_addr_hi32 = (uint64_t)start_addr >> 32;
     }
 
-    /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
-    machine->fdt = s->fdt;
-
     /* reset vector */
     uint32_t reset_vec[12] = {
         s->msel,                       /* MSEL pin state */
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e680d61ece..4a8828a30e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -67,9 +67,6 @@ typedef struct SiFiveUState {
     /*< public >*/
     SiFiveUSoCState soc;
 
-    void *fdt;
-    int fdt_size;
-
     bool start_in_flash;
     uint32_t msel;
     uint32_t serial;
-- 
2.39.0



  parent reply	other threads:[~2023-01-02 11:53 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-02 11:52 [PATCH v5 00/11] riscv: OpenSBI boot test and cleanups Daniel Henrique Barboza
2023-01-02 11:52 ` [PATCH v5 01/11] tests/avocado: add RISC-V OpenSBI boot test Daniel Henrique Barboza
2023-01-10 22:28   ` Alistair Francis
2023-01-02 11:52 ` [PATCH v5 02/11] hw/riscv/spike: use 'fdt' from MachineState Daniel Henrique Barboza
2023-01-02 11:52 ` Daniel Henrique Barboza [this message]
2023-01-02 11:52 ` [PATCH v5 04/11] hw/riscv/boot.c: exit early if filename is NULL in load functions Daniel Henrique Barboza
2023-01-08  3:30   ` Bin Meng
2023-01-10 22:29   ` Alistair Francis
2023-01-02 11:52 ` [PATCH v5 05/11] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Daniel Henrique Barboza
2023-01-02 11:52 ` [PATCH v5 06/11] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Daniel Henrique Barboza
2023-01-10 22:35   ` Alistair Francis
2023-01-02 11:52 ` [PATCH v5 07/11] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Daniel Henrique Barboza
2023-01-10 22:37   ` Alistair Francis
2023-01-02 11:52 ` [PATCH v5 08/11] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Daniel Henrique Barboza
2023-01-10 22:39   ` Alistair Francis
2023-01-02 11:52 ` [PATCH v5 09/11] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Daniel Henrique Barboza
2023-01-10 22:40   ` Alistair Francis
2023-01-02 11:52 ` [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
2023-01-08  3:33   ` Bin Meng
2023-01-10 11:43     ` Daniel Henrique Barboza
2023-01-10 20:20       ` Daniel Henrique Barboza
2023-01-10 22:45         ` Alistair Francis
2023-01-10 22:42   ` Alistair Francis
2023-01-12  0:34   ` Alistair Francis
2023-01-12 13:24     ` Daniel Henrique Barboza
2023-01-13  5:23     ` Bin Meng
2023-01-13  7:16     ` Philippe Mathieu-Daudé
2023-01-13 10:21       ` Daniel Henrique Barboza
2023-01-13 10:30         ` Bin Meng
2023-01-13 10:49           ` Daniel Henrique Barboza
2023-01-02 11:52 ` [PATCH v5 11/11] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
2023-01-10 22:41   ` Alistair Francis
2023-01-11  5:08 ` [PATCH v5 00/11] riscv: OpenSBI boot test and cleanups Alistair Francis

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