From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Ira Weiny <ira.weiny@intel.com>
Cc: Michael Tsirkin <mst@redhat.com>,
Ben Widawsky <bwidawsk@kernel.org>, <qemu-devel@nongnu.org>,
<linux-cxl@vger.kernel.org>,
Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v2 7/8] bswap: Add the ability to store to an unaligned 24 bit field
Date: Tue, 3 Jan 2023 17:14:51 +0000 [thread overview]
Message-ID: <20230103171451.00005a91@huawei.com> (raw)
In-Reply-To: <20221221-ira-cxl-events-2022-11-17-v2-7-2ce2ecc06219@intel.com>
On Wed, 21 Dec 2022 20:24:37 -0800
Ira Weiny <ira.weiny@intel.com> wrote:
> CXL has 24 bit unaligned fields which need to be stored to. CXL is
> specified as little endian.
>
> Define st24_le_p() and the supporting functions to store such a field
> from a 32 bit host native value.
>
> The use of b, w, l, q as the size specifier is limiting. So "24" was
> used for the size part of the function name.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Hi Ira,
Whilst this seems good to me, it's buried deep in a CXL specific
patch set so I'm thinking it might not get the review it needs.
Perhaps we are better off starting with a local implementation then
posting a follow up series that introduces this an makes use of it
in the CXL code?
One comment inline.
Jonathan
> ---
> include/qemu/bswap.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
> index e1eca22f2548..8af4d4a75eb6 100644
> --- a/include/qemu/bswap.h
> +++ b/include/qemu/bswap.h
> @@ -25,6 +25,13 @@ static inline uint16_t bswap16(uint16_t x)
> return bswap_16(x);
> }
>
> +static inline uint32_t bswap24(uint32_t x)
> +{
> + return (((x & 0x000000ffU) << 16) |
> + ((x & 0x0000ff00U) << 0) |
> + ((x & 0x00ff0000U) >> 16));
> +}
> +
> static inline uint32_t bswap32(uint32_t x)
> {
> return bswap_32(x);
> @@ -43,6 +50,13 @@ static inline uint16_t bswap16(uint16_t x)
> ((x & 0xff00) >> 8));
> }
>
> +static inline uint32_t bswap24(uint32_t x)
> +{
> + return (((x & 0x000000ffU) << 16) |
> + ((x & 0x0000ff00U) << 0) |
> + ((x & 0x00ff0000U) >> 16));
> +}
Whilst I can see the logic in having two copies to keep it in a sensible
place wrt to the other implementations, neither of these is from byteswap
so I'd just drop it out of the ifdef and have just the one copy.
> +
> static inline uint32_t bswap32(uint32_t x)
> {
> return (((x & 0x000000ffU) << 24) |
> @@ -72,6 +86,11 @@ static inline void bswap16s(uint16_t *s)
> *s = bswap16(*s);
> }
>
> +static inline void bswap24s(uint32_t *s)
> +{
> + *s = bswap24(*s);
> +}
> +
> static inline void bswap32s(uint32_t *s)
> {
> *s = bswap32(*s);
> @@ -233,6 +252,7 @@ CPU_CONVERT(le, 64, uint64_t)
> * size is:
> * b: 8 bits
> * w: 16 bits
> + * 24: 24 bits
> * l: 32 bits
> * q: 64 bits
> *
> @@ -305,6 +325,11 @@ static inline void stw_he_p(void *ptr, uint16_t v)
> __builtin_memcpy(ptr, &v, sizeof(v));
> }
>
> +static inline void st24_he_p(void *ptr, uint32_t v)
> +{
> + __builtin_memcpy(ptr, &v, 3);
> +}
> +
> static inline int ldl_he_p(const void *ptr)
> {
> int32_t r;
> @@ -354,6 +379,11 @@ static inline void stw_le_p(void *ptr, uint16_t v)
> stw_he_p(ptr, le_bswap(v, 16));
> }
>
> +static inline void st24_le_p(void *ptr, uint32_t v)
> +{
> + st24_he_p(ptr, le_bswap(v, 24));
> +}
> +
> static inline void stl_le_p(void *ptr, uint32_t v)
> {
> stl_he_p(ptr, le_bswap(v, 32));
>
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Ira Weiny <ira.weiny@intel.com>
Cc: Michael Tsirkin <mst@redhat.com>,
Ben Widawsky <bwidawsk@kernel.org>, <qemu-devel@nongnu.org>,
<linux-cxl@vger.kernel.org>,
Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v2 7/8] bswap: Add the ability to store to an unaligned 24 bit field
Date: Tue, 3 Jan 2023 17:14:51 +0000 [thread overview]
Message-ID: <20230103171451.00005a91@huawei.com> (raw)
In-Reply-To: <20221221-ira-cxl-events-2022-11-17-v2-7-2ce2ecc06219@intel.com>
On Wed, 21 Dec 2022 20:24:37 -0800
Ira Weiny <ira.weiny@intel.com> wrote:
> CXL has 24 bit unaligned fields which need to be stored to. CXL is
> specified as little endian.
>
> Define st24_le_p() and the supporting functions to store such a field
> from a 32 bit host native value.
>
> The use of b, w, l, q as the size specifier is limiting. So "24" was
> used for the size part of the function name.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Hi Ira,
Whilst this seems good to me, it's buried deep in a CXL specific
patch set so I'm thinking it might not get the review it needs.
Perhaps we are better off starting with a local implementation then
posting a follow up series that introduces this an makes use of it
in the CXL code?
One comment inline.
Jonathan
> ---
> include/qemu/bswap.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
> index e1eca22f2548..8af4d4a75eb6 100644
> --- a/include/qemu/bswap.h
> +++ b/include/qemu/bswap.h
> @@ -25,6 +25,13 @@ static inline uint16_t bswap16(uint16_t x)
> return bswap_16(x);
> }
>
> +static inline uint32_t bswap24(uint32_t x)
> +{
> + return (((x & 0x000000ffU) << 16) |
> + ((x & 0x0000ff00U) << 0) |
> + ((x & 0x00ff0000U) >> 16));
> +}
> +
> static inline uint32_t bswap32(uint32_t x)
> {
> return bswap_32(x);
> @@ -43,6 +50,13 @@ static inline uint16_t bswap16(uint16_t x)
> ((x & 0xff00) >> 8));
> }
>
> +static inline uint32_t bswap24(uint32_t x)
> +{
> + return (((x & 0x000000ffU) << 16) |
> + ((x & 0x0000ff00U) << 0) |
> + ((x & 0x00ff0000U) >> 16));
> +}
Whilst I can see the logic in having two copies to keep it in a sensible
place wrt to the other implementations, neither of these is from byteswap
so I'd just drop it out of the ifdef and have just the one copy.
> +
> static inline uint32_t bswap32(uint32_t x)
> {
> return (((x & 0x000000ffU) << 24) |
> @@ -72,6 +86,11 @@ static inline void bswap16s(uint16_t *s)
> *s = bswap16(*s);
> }
>
> +static inline void bswap24s(uint32_t *s)
> +{
> + *s = bswap24(*s);
> +}
> +
> static inline void bswap32s(uint32_t *s)
> {
> *s = bswap32(*s);
> @@ -233,6 +252,7 @@ CPU_CONVERT(le, 64, uint64_t)
> * size is:
> * b: 8 bits
> * w: 16 bits
> + * 24: 24 bits
> * l: 32 bits
> * q: 64 bits
> *
> @@ -305,6 +325,11 @@ static inline void stw_he_p(void *ptr, uint16_t v)
> __builtin_memcpy(ptr, &v, sizeof(v));
> }
>
> +static inline void st24_he_p(void *ptr, uint32_t v)
> +{
> + __builtin_memcpy(ptr, &v, 3);
> +}
> +
> static inline int ldl_he_p(const void *ptr)
> {
> int32_t r;
> @@ -354,6 +379,11 @@ static inline void stw_le_p(void *ptr, uint16_t v)
> stw_he_p(ptr, le_bswap(v, 16));
> }
>
> +static inline void st24_le_p(void *ptr, uint32_t v)
> +{
> + st24_he_p(ptr, le_bswap(v, 24));
> +}
> +
> static inline void stl_le_p(void *ptr, uint32_t v)
> {
> stl_he_p(ptr, le_bswap(v, 32));
>
next prev parent reply other threads:[~2023-01-03 17:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-22 4:24 [PATCH v2 0/8] QEMU CXL Provide mock CXL events and irq support Ira Weiny
2022-12-22 4:24 ` [PATCH v2 1/8] qemu/bswap: Add const_le64() Ira Weiny
2022-12-22 4:24 ` [PATCH v2 2/8] qemu/uuid: Add UUID static initializer Ira Weiny
2022-12-22 4:24 ` [PATCH v2 3/8] hw/cxl/mailbox: Use new UUID network order define for cel_uuid Ira Weiny
2023-01-03 16:30 ` Jonathan Cameron
2023-01-03 16:30 ` Jonathan Cameron via
2022-12-22 4:24 ` [PATCH v2 4/8] hw/cxl/events: Add event status register Ira Weiny
2023-01-03 16:36 ` Jonathan Cameron
2023-01-03 16:36 ` Jonathan Cameron via
2022-12-22 4:24 ` [PATCH v2 5/8] hw/cxl/events: Wire up get/clear event mailbox commands Ira Weiny
2023-01-04 18:07 ` Jonathan Cameron
2023-01-04 18:07 ` Jonathan Cameron via
2023-01-24 17:04 ` Jonathan Cameron
2023-01-24 17:04 ` Jonathan Cameron via
2022-12-22 4:24 ` [PATCH v2 6/8] hw/cxl/events: Add event interrupt support Ira Weiny
2022-12-22 4:24 ` [PATCH v2 7/8] bswap: Add the ability to store to an unaligned 24 bit field Ira Weiny
2023-01-03 17:14 ` Jonathan Cameron [this message]
2023-01-03 17:14 ` Jonathan Cameron via
2022-12-22 4:24 ` [PATCH v2 8/8] hw/cxl/events: Add in inject general media event Ira Weiny
2023-01-03 18:07 ` Jonathan Cameron
2023-01-03 18:07 ` Jonathan Cameron via
2023-01-09 19:15 ` Ira Weiny
2023-01-10 15:38 ` Jonathan Cameron
2023-01-10 15:38 ` Jonathan Cameron via
2023-01-11 14:05 ` Jonathan Cameron
2023-01-11 14:05 ` Jonathan Cameron via
2023-01-12 15:34 ` Jonathan Cameron
2023-01-12 15:34 ` Jonathan Cameron via
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