[PATCH 1/9] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY

[PATCH 1/9] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY

[Robert Marko]

Serdes register space sizes are incorrect, update them to match the
actual sizes from downstream QCA 5.4 kernel.

Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 4b4cd3eaf6c8..6649a758d8df 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -277,9 +277,9 @@ pcie_qmp1: phy@8e000 {
 			status = "disabled";
 
 			pcie_phy1: phy@8e200 {
-				reg = <0x8e200 0x16c>,
+				reg = <0x8e200 0x130>,
 				      <0x8e400 0x200>,
-				      <0x8e800 0x4f4>;
+				      <0x8e800 0x1f8>;
 				#phy-cells = <0>;
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-- 
2.38.1

[PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Robert Marko]

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the
kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start
and size, add the missing misc PCS register space.

Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 6649a758d8df..9503dfb25d50 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 {
 			status = "disabled";
 		};
 
-		pcie_qmp0: phy@86000 {
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
-			reg = <0x00086000 0x1c4>;
+		pcie_qmp0: phy@84000 {
+			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
+			reg = <0x00084000 0x1bc>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 {
 				      "common";
 			status = "disabled";
 
-			pcie_phy0: phy@86200 {
-				reg = <0x86200 0x16c>,
-				      <0x86400 0x200>,
-				      <0x86800 0x4f4>;
+			pcie_phy0: phy@84200 {
+				reg = <0x84200 0x16c>,
+				      <0x84400 0x200>,
+				      <0x84800 0x1f0>,
+				      <0x84c00 0xf4>;
 				#phy-cells = <0>;
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-- 
2.38.1

Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Bjorn Andersson]

On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> IPQ8074 comes in 2 silicon versions:
> * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> 
> v2 is the final and production version that is actually supported by the
> kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> 
> Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> by fixing the Gen3 QMP PHY node first.
> 
> Change the compatible to the Gen3 QMP PHY, correct the register space start
> and size, add the missing misc PCS register space.
> 

Does this imply that the current node doesn't actually work?

If that's the case, could we perhaps adopt Johan Hovolds' new binding
and drop the subnode in favor of just a flat reg covering the whole
QMP region?

Regards,
Bjorn

> Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 6649a758d8df..9503dfb25d50 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 {
>  			status = "disabled";
>  		};
>  
> -		pcie_qmp0: phy@86000 {
> -			compatible = "qcom,ipq8074-qmp-pcie-phy";
> -			reg = <0x00086000 0x1c4>;
> +		pcie_qmp0: phy@84000 {
> +			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
> +			reg = <0x00084000 0x1bc>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> @@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 {
>  				      "common";
>  			status = "disabled";
>  
> -			pcie_phy0: phy@86200 {
> -				reg = <0x86200 0x16c>,
> -				      <0x86400 0x200>,
> -				      <0x86800 0x4f4>;
> +			pcie_phy0: phy@84200 {
> +				reg = <0x84200 0x16c>,
> +				      <0x84400 0x200>,
> +				      <0x84800 0x1f0>,
> +				      <0x84c00 0xf4>;
>  				#phy-cells = <0>;
>  				#clock-cells = <0>;
>  				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> -- 
> 2.38.1
> 

Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Robert Marko]

On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> > IPQ8074 comes in 2 silicon versions:
> > * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> >
> > v2 is the final and production version that is actually supported by the
> > kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> >
> > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> > by fixing the Gen3 QMP PHY node first.
> >
> > Change the compatible to the Gen3 QMP PHY, correct the register space start
> > and size, add the missing misc PCS register space.
> >
>
> Does this imply that the current node doesn't actually work?

Hi Bjorn,
Yes, the node is for a completely different PHY generation, basically
PCIe on IPQ8074
is completely broken, hence this patch series.

>
> If that's the case, could we perhaps adopt Johan Hovolds' new binding
> and drop the subnode in favor of just a flat reg covering the whole
> QMP region?

I have not seen that so far, any examples?

Regards,
Robert
>
> Regards,
> Bjorn
>
> > Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > ---
> >  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
> >  1 file changed, 8 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > index 6649a758d8df..9503dfb25d50 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > @@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 {
> >                       status = "disabled";
> >               };
> >
> > -             pcie_qmp0: phy@86000 {
> > -                     compatible = "qcom,ipq8074-qmp-pcie-phy";
> > -                     reg = <0x00086000 0x1c4>;
> > +             pcie_qmp0: phy@84000 {
> > +                     compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
> > +                     reg = <0x00084000 0x1bc>;
> >                       #address-cells = <1>;
> >                       #size-cells = <1>;
> >                       ranges;
> > @@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 {
> >                                     "common";
> >                       status = "disabled";
> >
> > -                     pcie_phy0: phy@86200 {
> > -                             reg = <0x86200 0x16c>,
> > -                                   <0x86400 0x200>,
> > -                                   <0x86800 0x4f4>;
> > +                     pcie_phy0: phy@84200 {
> > +                             reg = <0x84200 0x16c>,
> > +                                   <0x84400 0x200>,
> > +                                   <0x84800 0x1f0>,
> > +                                   <0x84c00 0xf4>;
> >                               #phy-cells = <0>;
> >                               #clock-cells = <0>;
> >                               clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> > --
> > 2.38.1
> >

Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Bjorn Andersson]

On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote:
> On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote:
> >
> > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> > > IPQ8074 comes in 2 silicon versions:
> > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> > >
> > > v2 is the final and production version that is actually supported by the
> > > kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> > >
> > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> > > by fixing the Gen3 QMP PHY node first.
> > >
> > > Change the compatible to the Gen3 QMP PHY, correct the register space start
> > > and size, add the missing misc PCS register space.
> > >
> >
> > Does this imply that the current node doesn't actually work?
> 
> Hi Bjorn,
> Yes, the node is for a completely different PHY generation, basically
> PCIe on IPQ8074
> is completely broken, hence this patch series.
> 
> >
> > If that's the case, could we perhaps adopt Johan Hovolds' new binding
> > and drop the subnode in favor of just a flat reg covering the whole
> > QMP region?
> 
> I have not seen that so far, any examples?
> 

See
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in
v6.2-rc1.

The idea is to, at least, use this for all new platforms introduced.

And if the current definition doesn't actually work I suggest that we
replace it with the new one.

Regards,
Bjorn

Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Robert Marko]

On Tue, 27 Dec 2022 at 20:20, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote:
> > On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote:
> > >
> > > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> > > > IPQ8074 comes in 2 silicon versions:
> > > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> > > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> > > >
> > > > v2 is the final and production version that is actually supported by the
> > > > kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> > > >
> > > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> > > > by fixing the Gen3 QMP PHY node first.
> > > >
> > > > Change the compatible to the Gen3 QMP PHY, correct the register space start
> > > > and size, add the missing misc PCS register space.
> > > >
> > >
> > > Does this imply that the current node doesn't actually work?
> >
> > Hi Bjorn,
> > Yes, the node is for a completely different PHY generation, basically
> > PCIe on IPQ8074
> > is completely broken, hence this patch series.
> >
> > >
> > > If that's the case, could we perhaps adopt Johan Hovolds' new binding
> > > and drop the subnode in favor of just a flat reg covering the whole
> > > QMP region?
> >
> > I have not seen that so far, any examples?
> >
>
> See
> Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in
> v6.2-rc1.
>
> The idea is to, at least, use this for all new platforms introduced.
>
> And if the current definition doesn't actually work I suggest that we
> replace it with the new one.

I understand the intention, but these bindings dont match the QMP generation
found in IPQ8074 at all, and Gen3 has already been documented in bindings.

This would require updating the driver to carry the offsets and rework
of bindings to
not require power domains, etc for IPQ8074 as I have not found any
code downstream
to indicate it has GSDC-s for PCIe though I dont have any docs at all
for the SoC.

Regards,
Robert
>
> Regards,
> Bjorn

Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Bjorn Andersson]

On Wed, Dec 28, 2022 at 12:10:17PM +0100, Robert Marko wrote:
> On Tue, 27 Dec 2022 at 20:20, Bjorn Andersson <andersson@kernel.org> wrote:
> >
> > On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote:
> > > On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote:
> > > >
> > > > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> > > > > IPQ8074 comes in 2 silicon versions:
> > > > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> > > > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> > > > >
> > > > > v2 is the final and production version that is actually supported by the
> > > > > kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> > > > >
> > > > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> > > > > by fixing the Gen3 QMP PHY node first.
> > > > >
> > > > > Change the compatible to the Gen3 QMP PHY, correct the register space start
> > > > > and size, add the missing misc PCS register space.
> > > > >
> > > >
> > > > Does this imply that the current node doesn't actually work?
> > >
> > > Hi Bjorn,
> > > Yes, the node is for a completely different PHY generation, basically
> > > PCIe on IPQ8074
> > > is completely broken, hence this patch series.
> > >
> > > >
> > > > If that's the case, could we perhaps adopt Johan Hovolds' new binding
> > > > and drop the subnode in favor of just a flat reg covering the whole
> > > > QMP region?
> > >
> > > I have not seen that so far, any examples?
> > >
> >
> > See
> > Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in
> > v6.2-rc1.
> >
> > The idea is to, at least, use this for all new platforms introduced.
> >
> > And if the current definition doesn't actually work I suggest that we
> > replace it with the new one.
> 
> I understand the intention, but these bindings dont match the QMP generation
> found in IPQ8074 at all, and Gen3 has already been documented in bindings.
> 
> This would require updating the driver to carry the offsets and rework
> of bindings to
> not require power domains, etc for IPQ8074 as I have not found any
> code downstream
> to indicate it has GSDC-s for PCIe though I dont have any docs at all
> for the SoC.
> 

I was only thinking of the structural difference, not the power-domains
etc. But yes you're right that it means updating the driver and the
binding.

The end result would be much nicer though...

Regards,
Bjorn

Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY

[Robert Marko]

On Thu, 29 Dec 2022 at 18:29, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Wed, Dec 28, 2022 at 12:10:17PM +0100, Robert Marko wrote:
> > On Tue, 27 Dec 2022 at 20:20, Bjorn Andersson <andersson@kernel.org> wrote:
> > >
> > > On Tue, Dec 06, 2022 at 10:51:40AM +0100, Robert Marko wrote:
> > > > On Mon, 5 Dec 2022 at 22:52, Bjorn Andersson <andersson@kernel.org> wrote:
> > > > >
> > > > > On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> > > > > > IPQ8074 comes in 2 silicon versions:
> > > > > > * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> > > > > > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> > > > > >
> > > > > > v2 is the final and production version that is actually supported by the
> > > > > > kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> > > > > >
> > > > > > Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> > > > > > by fixing the Gen3 QMP PHY node first.
> > > > > >
> > > > > > Change the compatible to the Gen3 QMP PHY, correct the register space start
> > > > > > and size, add the missing misc PCS register space.
> > > > > >
> > > > >
> > > > > Does this imply that the current node doesn't actually work?
> > > >
> > > > Hi Bjorn,
> > > > Yes, the node is for a completely different PHY generation, basically
> > > > PCIe on IPQ8074
> > > > is completely broken, hence this patch series.
> > > >
> > > > >
> > > > > If that's the case, could we perhaps adopt Johan Hovolds' new binding
> > > > > and drop the subnode in favor of just a flat reg covering the whole
> > > > > QMP region?
> > > >
> > > > I have not seen that so far, any examples?
> > > >
> > >
> > > See
> > > Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in
> > > v6.2-rc1.
> > >
> > > The idea is to, at least, use this for all new platforms introduced.
> > >
> > > And if the current definition doesn't actually work I suggest that we
> > > replace it with the new one.
> >
> > I understand the intention, but these bindings dont match the QMP generation
> > found in IPQ8074 at all, and Gen3 has already been documented in bindings.
> >
> > This would require updating the driver to carry the offsets and rework
> > of bindings to
> > not require power domains, etc for IPQ8074 as I have not found any
> > code downstream
> > to indicate it has GSDC-s for PCIe though I dont have any docs at all
> > for the SoC.
> >
>
> I was only thinking of the structural difference, not the power-domains
> etc. But yes you're right that it means updating the driver and the
> binding.
>
> The end result would be much nicer though...

I agree that it would be nicer, though it's asking for many changes, especially
bindings since it's already described there.

The current patchset has been thoroughly tested for months at this point.

How would you like to proceed here, as I would really like to get PCI working
upstream?

Regards,
Robert
>
> Regards,
> Bjorn

[PATCH 3/9] arm64: dts: qcom: ipq8074: correct Gen2 PCIe ranges

[Robert Marko]

Current ranges property set in Gen2 PCIe node is incorrect, replace it
with the downstream 5.4 QCA kernel value.

Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 9503dfb25d50..b1decedbd080 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -808,9 +808,9 @@ pcie1: pci@10000000 {
 			phy-names = "pciephy";
 
 			ranges = <0x81000000 0 0x10200000 0x10200000
-				  0 0x100000   /* downstream I/O */
-				  0x82000000 0 0x10300000 0x10300000
-				  0 0xd00000>; /* non-prefetchable memory */
+				  0 0x10000>,   /* downstream I/O */
+				 <0x82000000 0 0x10220000 0x10220000
+				  0 0xfde0000>; /* non-prefetchable memory */
 
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi";
-- 
2.38.1

[PATCH 4/9] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed

[Robert Marko]

Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
generation limit.
This allows the generic DWC code to configure the link speed correctly.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index b1decedbd080..585e5f0a139d 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -801,6 +801,7 @@ pcie1: pci@10000000 {
 			linux,pci-domain = <1>;
 			bus-range = <0x00 0xff>;
 			num-lanes = <1>;
+			max-link-speed = <2>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 
-- 
2.38.1

[PATCH 5/9] dt-bindings: PCI: qcom: alphabetically sort compatibles

[Robert Marko]

Sort the compatibles list alphabetically for maintenance.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 2f851c804bb0..1e94c210429a 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -17,13 +17,14 @@ description: |
 properties:
   compatible:
     enum:
-      - qcom,pcie-ipq8064
-      - qcom,pcie-ipq8064-v2
       - qcom,pcie-apq8064
       - qcom,pcie-apq8084
-      - qcom,pcie-msm8996
       - qcom,pcie-ipq4019
+      - qcom,pcie-ipq6018
+      - qcom,pcie-ipq8064
+      - qcom,pcie-ipq8064-v2
       - qcom,pcie-ipq8074
+      - qcom,pcie-msm8996
       - qcom,pcie-qcs404
       - qcom,pcie-sa8540p
       - qcom,pcie-sc7280
@@ -34,7 +35,6 @@ properties:
       - qcom,pcie-sm8250
       - qcom,pcie-sm8450-pcie0
       - qcom,pcie-sm8450-pcie1
-      - qcom,pcie-ipq6018
 
   reg:
     minItems: 4
-- 
2.38.1

Re: [PATCH 5/9] dt-bindings: PCI: qcom: alphabetically sort compatibles

[Krzysztof Kozlowski]

On 16/11/2022 22:48, Robert Marko wrote:
> Sort the compatibles list alphabetically for maintenance.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++----


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 5/9] dt-bindings: PCI: qcom: alphabetically sort compatibles

[Manivannan Sadhasivam]

On Wed, Nov 16, 2022 at 10:48:37PM +0100, Robert Marko wrote:
> Sort the compatibles list alphabetically for maintenance.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Thanks,
Mani

> ---
>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 2f851c804bb0..1e94c210429a 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -17,13 +17,14 @@ description: |
>  properties:
>    compatible:
>      enum:
> -      - qcom,pcie-ipq8064
> -      - qcom,pcie-ipq8064-v2
>        - qcom,pcie-apq8064
>        - qcom,pcie-apq8084
> -      - qcom,pcie-msm8996
>        - qcom,pcie-ipq4019
> +      - qcom,pcie-ipq6018
> +      - qcom,pcie-ipq8064
> +      - qcom,pcie-ipq8064-v2
>        - qcom,pcie-ipq8074
> +      - qcom,pcie-msm8996
>        - qcom,pcie-qcs404
>        - qcom,pcie-sa8540p
>        - qcom,pcie-sc7280
> @@ -34,7 +35,6 @@ properties:
>        - qcom,pcie-sm8250
>        - qcom,pcie-sm8450-pcie0
>        - qcom,pcie-sm8450-pcie1
> -      - qcom,pcie-ipq6018
>  
>    reg:
>      minItems: 4
> -- 
> 2.38.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH 6/9] dt-bindings: PCI: qcom: document IPQ8074 Gen3 port

[Robert Marko]

IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported.
Document Gen3 port which uses the same controller as IPQ6018.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 1e94c210429a..59f4c9990f85 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -24,6 +24,7 @@ properties:
       - qcom,pcie-ipq8064
       - qcom,pcie-ipq8064-v2
       - qcom,pcie-ipq8074
+      - qcom,pcie-ipq8074-gen3
       - qcom,pcie-msm8996
       - qcom,pcie-qcs404
       - qcom,pcie-sa8540p
@@ -151,6 +152,7 @@ allOf:
           contains:
             enum:
               - qcom,pcie-ipq6018
+              - qcom,pcie-ipq8074-gen3
     then:
       properties:
         reg:
@@ -371,6 +373,7 @@ allOf:
           contains:
             enum:
               - qcom,pcie-ipq6018
+              - qcom,pcie-ipq8074-gen3
     then:
       properties:
         clocks:
@@ -662,6 +665,7 @@ allOf:
                 - qcom,pcie-ipq8064
                 - qcom,pcie-ipq8064v2
                 - qcom,pcie-ipq8074
+                - qcom,pcie-ipq8074-gen3
                 - qcom,pcie-qcs404
     then:
       required:
@@ -744,6 +748,7 @@ allOf:
               - qcom,pcie-ipq8064
               - qcom,pcie-ipq8064-v2
               - qcom,pcie-ipq8074
+              - qcom,pcie-ipq8074-gen3
               - qcom,pcie-qcs404
               - qcom,pcie-sa8540p
     then:
-- 
2.38.1

Re: [PATCH 6/9] dt-bindings: PCI: qcom: document IPQ8074 Gen3 port

[Krzysztof Kozlowski]

On 16/11/2022 22:48, Robert Marko wrote:
> IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported.
> Document Gen3 port which uses the same controller as IPQ6018.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 6/9] dt-bindings: PCI: qcom: document IPQ8074 Gen3 port

[Manivannan Sadhasivam]

On Wed, Nov 16, 2022 at 10:48:38PM +0100, Robert Marko wrote:
> IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported.
> Document Gen3 port which uses the same controller as IPQ6018.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Thanks,
Mani

> ---
>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 1e94c210429a..59f4c9990f85 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -24,6 +24,7 @@ properties:
>        - qcom,pcie-ipq8064
>        - qcom,pcie-ipq8064-v2
>        - qcom,pcie-ipq8074
> +      - qcom,pcie-ipq8074-gen3
>        - qcom,pcie-msm8996
>        - qcom,pcie-qcs404
>        - qcom,pcie-sa8540p
> @@ -151,6 +152,7 @@ allOf:
>            contains:
>              enum:
>                - qcom,pcie-ipq6018
> +              - qcom,pcie-ipq8074-gen3
>      then:
>        properties:
>          reg:
> @@ -371,6 +373,7 @@ allOf:
>            contains:
>              enum:
>                - qcom,pcie-ipq6018
> +              - qcom,pcie-ipq8074-gen3
>      then:
>        properties:
>          clocks:
> @@ -662,6 +665,7 @@ allOf:
>                  - qcom,pcie-ipq8064
>                  - qcom,pcie-ipq8064v2
>                  - qcom,pcie-ipq8074
> +                - qcom,pcie-ipq8074-gen3
>                  - qcom,pcie-qcs404
>      then:
>        required:
> @@ -744,6 +748,7 @@ allOf:
>                - qcom,pcie-ipq8064
>                - qcom,pcie-ipq8064-v2
>                - qcom,pcie-ipq8074
> +              - qcom,pcie-ipq8074-gen3
>                - qcom,pcie-qcs404
>                - qcom,pcie-sa8540p
>      then:
> -- 
> 2.38.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH 7/9] PCI: qcom: add support for IPQ8074 Gen3 port

[Robert Marko]

IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
Add compatible for Gen3 port which uses the same controller as IPQ6018.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 77e5dc7b88ad..97e8510c53fb 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
-- 
2.38.1

Re: [PATCH 7/9] PCI: qcom: add support for IPQ8074 Gen3 port

[Bjorn Helgaas]

Hi Robert,

If you post a v2 for any reason, capitalize the subject line to match
previous history:

  PCI: qcom: Rename host-init error label
  PCI: qcom: Drop unused post_deinit callback
  PCI: qcom: Sort device-id table
  PCI: qcom: Clean up IP configurations
  ...

On Wed, Nov 16, 2022 at 10:48:39PM +0100, Robert Marko wrote:
> IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
> Add compatible for Gen3 port which uses the same controller as IPQ6018.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 77e5dc7b88ad..97e8510c53fb 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>  	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
>  	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>  	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
> +	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>  	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
>  	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
>  	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
> -- 
> 2.38.1
> 

Re: [PATCH 7/9] PCI: qcom: add support for IPQ8074 Gen3 port

[Lorenzo Pieralisi]

On Thu, Nov 17, 2022 at 01:28:37PM -0600, Bjorn Helgaas wrote:
> Hi Robert,
> 
> If you post a v2 for any reason, capitalize the subject line to match
> previous history:
> 
>   PCI: qcom: Rename host-init error label
>   PCI: qcom: Drop unused post_deinit callback
>   PCI: qcom: Sort device-id table
>   PCI: qcom: Clean up IP configurations
>   ...

If he could do that while rebasing on top of my current pci/qcom branch
that would be ideal, I tried to cherry-pick patches 5,6,7 but 5 does not
apply.

Thanks,
Lorenzo

> 
> On Wed, Nov 16, 2022 at 10:48:39PM +0100, Robert Marko wrote:
> > IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
> > Add compatible for Gen3 port which uses the same controller as IPQ6018.
> > 
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 77e5dc7b88ad..97e8510c53fb 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> >  	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
> >  	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
> >  	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
> > +	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> >  	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
> >  	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
> >  	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
> > -- 
> > 2.38.1
> > 

Re: [PATCH 7/9] PCI: qcom: add support for IPQ8074 Gen3 port

[Robert Marko]

On Fri, 13 Jan 2023 at 14:34, Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>
> On Thu, Nov 17, 2022 at 01:28:37PM -0600, Bjorn Helgaas wrote:
> > Hi Robert,
> >
> > If you post a v2 for any reason, capitalize the subject line to match
> > previous history:
> >
> >   PCI: qcom: Rename host-init error label
> >   PCI: qcom: Drop unused post_deinit callback
> >   PCI: qcom: Sort device-id table
> >   PCI: qcom: Clean up IP configurations
> >   ...
>
> If he could do that while rebasing on top of my current pci/qcom branch
> that would be ideal, I tried to cherry-pick patches 5,6,7 but 5 does not
> apply.

Sure, I will send v2 with that now as after cherry-picking the SM8350 commits
from pci/qcom they all still apply, will fixup the subject capitalization.

Regards,
Robert
>
> Thanks,
> Lorenzo
>
> >
> > On Wed, Nov 16, 2022 at 10:48:39PM +0100, Robert Marko wrote:
> > > IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
> > > Add compatible for Gen3 port which uses the same controller as IPQ6018.
> > >
> > > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > > ---
> > >  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 77e5dc7b88ad..97e8510c53fb 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> > >     { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
> > >     { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
> > >     { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
> > > +   { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> > >     { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
> > >     { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
> > >     { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
> > > --
> > > 2.38.1
> > >

Re: [PATCH 7/9] PCI: qcom: add support for IPQ8074 Gen3 port

[Manivannan Sadhasivam]

On Wed, Nov 16, 2022 at 10:48:39PM +0100, Robert Marko wrote:
> IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
> Add compatible for Gen3 port which uses the same controller as IPQ6018.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Thanks,
Mani

> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 77e5dc7b88ad..97e8510c53fb 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>  	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
>  	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>  	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
> +	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>  	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
>  	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
>  	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
> -- 
> 2.38.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH 8/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node

[Robert Marko]

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the
kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Finish the PCIe fixup by using the correct compatible, adding missing ATU
register space, declaring max-link-speed, use correct ranges, add missing
clocks and resets.

Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 30 +++++++++++++++------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 585e5f0a139d..c76c6ee9acb6 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -854,16 +854,18 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 		};
 
 		pcie0: pci@20000000 {
-			compatible = "qcom,pcie-ipq8074";
+			compatible = "qcom,pcie-ipq8074-gen3";
 			reg = <0x20000000 0xf1d>,
 			      <0x20000f20 0xa8>,
-			      <0x00080000 0x2000>,
+			      <0x20001000 0x1000>,
+			      <0x00080000 0x4000>,
 			      <0x20100000 0x1000>;
-			reg-names = "dbi", "elbi", "parf", "config";
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
 			device_type = "pci";
 			linux,pci-domain = <0>;
 			bus-range = <0x00 0xff>;
 			num-lanes = <1>;
+			max-link-speed = <3>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 
@@ -871,9 +873,9 @@ pcie0: pci@20000000 {
 			phy-names = "pciephy";
 
 			ranges = <0x81000000 0 0x20200000 0x20200000
-				  0 0x100000   /* downstream I/O */
-				  0x82000000 0 0x20300000 0x20300000
-				  0 0xd00000>; /* non-prefetchable memory */
+				  0 0x10000>, /* downstream I/O */
+				 <0x82000000 0 0x20220000 0x20220000
+				  0 0xfde0000>; /* non-prefetchable memory */
 
 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi";
@@ -891,28 +893,30 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 				 <&gcc GCC_PCIE0_AXI_M_CLK>,
 				 <&gcc GCC_PCIE0_AXI_S_CLK>,
-				 <&gcc GCC_PCIE0_AHB_CLK>,
-				 <&gcc GCC_PCIE0_AUX_CLK>;
-
+				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE0_RCHNG_CLK>;
 			clock-names = "iface",
 				      "axi_m",
 				      "axi_s",
-				      "ahb",
-				      "aux";
+				      "axi_bridge",
+				      "rchng";
+
 			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 				 <&gcc GCC_PCIE0_SLEEP_ARES>,
 				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 				 <&gcc GCC_PCIE0_AHB_ARES>,
-				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 			reset-names = "pipe",
 				      "sleep",
 				      "sticky",
 				      "axi_m",
 				      "axi_s",
 				      "ahb",
-				      "axi_m_sticky";
+				      "axi_m_sticky",
+				      "axi_s_sticky";
 			status = "disabled";
 		};
 	};
-- 
2.38.1

[PATCH 9/9] arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock names

[Robert Marko]

Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
driver is relying on the old names to match them as they are being used as
the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.

This broke parenting as GCC could not find the parent clock, so fix it by
changing to the names that driver is expecting.

Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index c76c6ee9acb6..6f5d447c9ee7 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -257,7 +257,7 @@ pcie_phy0: phy@84200 {
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 				clock-names = "pipe0";
-				clock-output-names = "pcie_0_pipe_clk";
+				clock-output-names = "pcie20_phy0_pipe_clk";
 			};
 		};
 
@@ -285,7 +285,7 @@ pcie_phy1: phy@8e200 {
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 				clock-names = "pipe0";
-				clock-output-names = "pcie_1_pipe_clk";
+				clock-output-names = "pcie20_phy1_pipe_clk";
 			};
 		};
 
-- 
2.38.1