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From: Achal Verma <a-verma1@ti.com>
To: <mranostay@ti.com>, <rogerq@kernel.org>, <lpieralisi@kernel.org>,
	<robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>,
	<krzysztof.kozlowski@linaro.org>, <vigneshr@ti.com>,
	<tjoseph@cadence.com>, <sergio.paracuellos@gmail.com>,
	<pthombar@cadence.com>, <linux-pci@vger.kernel.org>
Cc: <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-omap@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v8 3/5] PCI: j721e: Add PCIe 4x lane selection support
Date: Wed, 18 Jan 2023 18:29:34 +0530	[thread overview]
Message-ID: <20230118125936.3456716-4-a-verma1@ti.com> (raw)
In-Reply-To: <20230118125936.3456716-1-a-verma1@ti.com>

From: Matt Ranostay <mranostay@ti.com>

Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Achal Verma <a-verma1@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index f4dc2c5abedb..58dcac9021e4 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -42,7 +42,6 @@ enum link_status {
 };
 
 #define J721E_MODE_RC			BIT(7)
-#define LANE_COUNT_MASK			BIT(8)
 #define LANE_COUNT(n)			((n) << 8)
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
@@ -52,6 +51,7 @@ struct j721e_pcie {
 	struct clk		*refclk;
 	u32			mode;
 	u32			num_lanes;
+	u32			max_lanes;
 	void __iomem		*user_cfg_base;
 	void __iomem		*intd_cfg_base;
 	u32			linkdown_irq_regfield;
@@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
 {
 	struct device *dev = pcie->cdns_pcie->dev;
 	u32 lanes = pcie->num_lanes;
+	u32 mask = BIT(8);
 	u32 val = 0;
 	int ret;
 
+	if (pcie->max_lanes == 4)
+		mask = GENMASK(9, 8);
+
 	val = LANE_COUNT(lanes - 1);
-	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+	ret = regmap_update_bits(syscon, offset, mask, val);
 	if (ret)
 		dev_err(dev, "failed to set link count\n");
 
@@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 		dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
 		num_lanes = 1;
 	}
+
 	pcie->num_lanes = num_lanes;
+	pcie->max_lanes = data->max_lanes;
 
 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
 		return -EINVAL;
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Achal Verma <a-verma1@ti.com>
To: <mranostay@ti.com>, <rogerq@kernel.org>, <lpieralisi@kernel.org>,
	<robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>,
	<krzysztof.kozlowski@linaro.org>, <vigneshr@ti.com>,
	<tjoseph@cadence.com>, <sergio.paracuellos@gmail.com>,
	<pthombar@cadence.com>, <linux-pci@vger.kernel.org>
Cc: <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-omap@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v8 3/5] PCI: j721e: Add PCIe 4x lane selection support
Date: Wed, 18 Jan 2023 18:29:34 +0530	[thread overview]
Message-ID: <20230118125936.3456716-4-a-verma1@ti.com> (raw)
In-Reply-To: <20230118125936.3456716-1-a-verma1@ti.com>

From: Matt Ranostay <mranostay@ti.com>

Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Achal Verma <a-verma1@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index f4dc2c5abedb..58dcac9021e4 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -42,7 +42,6 @@ enum link_status {
 };
 
 #define J721E_MODE_RC			BIT(7)
-#define LANE_COUNT_MASK			BIT(8)
 #define LANE_COUNT(n)			((n) << 8)
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
@@ -52,6 +51,7 @@ struct j721e_pcie {
 	struct clk		*refclk;
 	u32			mode;
 	u32			num_lanes;
+	u32			max_lanes;
 	void __iomem		*user_cfg_base;
 	void __iomem		*intd_cfg_base;
 	u32			linkdown_irq_regfield;
@@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
 {
 	struct device *dev = pcie->cdns_pcie->dev;
 	u32 lanes = pcie->num_lanes;
+	u32 mask = BIT(8);
 	u32 val = 0;
 	int ret;
 
+	if (pcie->max_lanes == 4)
+		mask = GENMASK(9, 8);
+
 	val = LANE_COUNT(lanes - 1);
-	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+	ret = regmap_update_bits(syscon, offset, mask, val);
 	if (ret)
 		dev_err(dev, "failed to set link count\n");
 
@@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 		dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
 		num_lanes = 1;
 	}
+
 	pcie->num_lanes = num_lanes;
+	pcie->max_lanes = data->max_lanes;
 
 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
 		return -EINVAL;
-- 
2.25.1


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  parent reply	other threads:[~2023-01-18 13:33 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-18 12:59 [PATCH v8 0/5] PCI: add 4x lane support for pci-j721e controllers Achal Verma
2023-01-18 12:59 ` Achal Verma
2023-01-18 12:59 ` [PATCH v8 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Achal Verma
2023-01-18 12:59   ` Achal Verma
2023-01-19 15:38   ` Krzysztof Kozlowski
2023-01-19 15:38     ` Krzysztof Kozlowski
2023-01-18 12:59 ` [PATCH v8 2/5] PCI: j721e: Add per platform maximum lane settings Achal Verma
2023-01-18 12:59   ` Achal Verma
2023-01-18 12:59 ` Achal Verma [this message]
2023-01-18 12:59   ` [PATCH v8 3/5] PCI: j721e: Add PCIe 4x lane selection support Achal Verma
2023-01-18 12:59 ` [PATCH v8 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Achal Verma
2023-01-18 12:59   ` Achal Verma
2023-01-18 12:59 ` [PATCH v8 5/5] PCI: j721e: add j784s4 PCIe configuration Achal Verma
2023-01-18 12:59   ` Achal Verma
2023-01-18 16:56   ` Bjorn Helgaas
2023-01-18 16:56     ` Bjorn Helgaas

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