From: Shawn Guo <shawnguo@kernel.org>
To: Marek Vasut <marex@denx.de>
Cc: linux-arm-kernel@lists.infradead.org,
Christoph Niedermaier <cniedermaier@dh-electronics.com>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
devicetree@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM
Date: Thu, 26 Jan 2023 15:51:33 +0800 [thread overview]
Message-ID: <20230126075132.GA20713@T480> (raw)
In-Reply-To: <20230117223942.130170-1-marex@denx.de>
On Tue, Jan 17, 2023 at 11:39:42PM +0100, Marek Vasut wrote:
> Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz
> instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which
> is the maximum supported baud rate by the muRata 2AE BT UART.
>
> The difference here is that at 64 MHz UART block clock, the clock with are
> divided by 16 (due to oversampling) to 4 MHz and the baud rate generator
> then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of
> 80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator
> needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps .
>
> Both options are valid and yield the same result, except using the PLL1_80M
> output requires fewer clock tree changes, since the PLL1 already generates
> the 80 MHz usable for UART, which frees the PLL3 for other uses.
>
> Suggested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied, thanks!
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WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Marek Vasut <marex@denx.de>
Cc: linux-arm-kernel@lists.infradead.org,
Christoph Niedermaier <cniedermaier@dh-electronics.com>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
devicetree@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM
Date: Thu, 26 Jan 2023 15:51:33 +0800 [thread overview]
Message-ID: <20230126075132.GA20713@T480> (raw)
In-Reply-To: <20230117223942.130170-1-marex@denx.de>
On Tue, Jan 17, 2023 at 11:39:42PM +0100, Marek Vasut wrote:
> Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz
> instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which
> is the maximum supported baud rate by the muRata 2AE BT UART.
>
> The difference here is that at 64 MHz UART block clock, the clock with are
> divided by 16 (due to oversampling) to 4 MHz and the baud rate generator
> then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of
> 80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator
> needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps .
>
> Both options are valid and yield the same result, except using the PLL1_80M
> output requires fewer clock tree changes, since the PLL1 already generates
> the 80 MHz usable for UART, which frees the PLL3 for other uses.
>
> Suggested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied, thanks!
next prev parent reply other threads:[~2023-01-26 7:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-17 22:39 [PATCH] arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM Marek Vasut
2023-01-17 22:39 ` Marek Vasut
2023-01-17 23:22 ` Fabio Estevam
2023-01-17 23:22 ` Fabio Estevam
2023-01-26 7:51 ` Shawn Guo [this message]
2023-01-26 7:51 ` Shawn Guo
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