From: Jisheng Zhang <jszhang@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
Date: Sun, 29 Jan 2023 01:28:49 +0800 [thread overview]
Message-ID: <20230128172856.3814-7-jszhang@kernel.org> (raw)
In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org>
Switch has_fpu() from static branch to the new helper
riscv_has_extension_likely().
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/switch_to.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 11463489fec6..60f8ca01d36e 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev,
static __always_inline bool has_fpu(void)
{
- return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
+ return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
+ riscv_has_extension_likely(RISCV_ISA_EXT_d);
}
#else
static __always_inline bool has_fpu(void) { return false; }
--
2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
Date: Sun, 29 Jan 2023 01:28:49 +0800 [thread overview]
Message-ID: <20230128172856.3814-7-jszhang@kernel.org> (raw)
In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org>
Switch has_fpu() from static branch to the new helper
riscv_has_extension_likely().
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/switch_to.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 11463489fec6..60f8ca01d36e 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev,
static __always_inline bool has_fpu(void)
{
- return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
+ return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
+ riscv_has_extension_likely(RISCV_ISA_EXT_d);
}
#else
static __always_inline bool has_fpu(void) { return false; }
--
2.38.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
Date: Sun, 29 Jan 2023 01:28:49 +0800 [thread overview]
Message-ID: <20230128172856.3814-7-jszhang@kernel.org> (raw)
In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org>
Switch has_fpu() from static branch to the new helper
riscv_has_extension_likely().
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/switch_to.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 11463489fec6..60f8ca01d36e 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev,
static __always_inline bool has_fpu(void)
{
- return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
+ return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
+ riscv_has_extension_likely(RISCV_ISA_EXT_d);
}
#else
static __always_inline bool has_fpu(void) { return false; }
--
2.38.1
next prev parent reply other threads:[~2023-01-28 17:28 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-28 17:28 [PATCH v5 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 01/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 02/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 03/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 05/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang [this message]
2023-01-28 17:28 ` [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-03-22 12:01 ` Jason A. Donenfeld
2023-03-22 12:01 ` Jason A. Donenfeld
2023-03-22 12:01 ` Jason A. Donenfeld
2023-03-22 12:09 ` [PATCH] riscv: require alternatives framework when selecting FPU support Jason A. Donenfeld
2023-03-22 12:09 ` Jason A. Donenfeld
2023-03-22 12:09 ` Jason A. Donenfeld
2023-03-22 12:46 ` Andrew Jones
2023-03-22 12:46 ` Andrew Jones
2023-03-22 12:46 ` Andrew Jones
2023-03-22 15:17 ` Conor Dooley
2023-03-22 15:17 ` Conor Dooley
2023-03-22 15:17 ` Conor Dooley
2023-03-22 19:26 ` Andrew Jones
2023-03-22 19:26 ` Andrew Jones
2023-03-22 19:26 ` Andrew Jones
2023-03-22 19:44 ` Conor Dooley
2023-03-22 19:44 ` Conor Dooley
2023-03-22 19:44 ` Conor Dooley
2023-03-22 20:05 ` Conor Dooley
2023-03-22 20:05 ` Conor Dooley
2023-03-22 20:05 ` Conor Dooley
2023-03-22 20:19 ` Jason A. Donenfeld
2023-03-22 20:19 ` Jason A. Donenfeld
2023-03-22 20:19 ` Jason A. Donenfeld
2023-03-23 14:49 ` Conor Dooley
2023-03-23 14:50 ` Conor Dooley
2023-03-23 14:49 ` Conor Dooley
2023-03-23 15:56 ` Jason A. Donenfeld
2023-03-23 15:56 ` Jason A. Donenfeld
2023-03-23 15:56 ` Jason A. Donenfeld
2023-03-23 22:19 ` Conor Dooley
2023-03-23 22:20 ` Conor Dooley
2023-03-23 22:19 ` Conor Dooley
2023-01-28 17:28 ` [PATCH v5 07/13] riscv: module: move find_section to module.h Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 08/13] riscv: module: Add ADD16 and SUB16 rela types Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 09/13] riscv: switch to relative alternative entries Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-01-28 17:28 ` Jisheng Zhang
2023-02-02 23:39 ` [PATCH v5 00/13] riscv: improve boot time isa extensions handling Palmer Dabbelt
2023-02-02 23:39 ` Palmer Dabbelt
2023-02-02 23:39 ` Palmer Dabbelt
2023-02-02 23:40 ` patchwork-bot+linux-riscv
2023-02-02 23:40 ` patchwork-bot+linux-riscv
2023-02-02 23:40 ` patchwork-bot+linux-riscv
2023-02-12 15:43 ` Guenter Roeck
2023-02-12 15:43 ` Guenter Roeck
2023-02-12 15:43 ` Guenter Roeck
2023-02-12 15:59 ` Conor Dooley
2023-02-12 16:00 ` Conor Dooley
2023-02-12 15:59 ` Conor Dooley
2023-02-12 16:33 ` Conor Dooley
2023-02-12 16:34 ` Conor Dooley
2023-02-12 16:33 ` Conor Dooley
2023-02-12 17:06 ` Conor Dooley
2023-02-12 17:06 ` Conor Dooley
2023-02-12 17:06 ` Conor Dooley
2023-02-12 18:06 ` Conor Dooley
2023-02-12 18:06 ` Conor Dooley
2023-02-12 18:06 ` Conor Dooley
2023-02-12 18:14 ` Guenter Roeck
2023-02-12 18:14 ` Guenter Roeck
2023-02-12 18:14 ` Guenter Roeck
2023-02-12 18:20 ` Conor Dooley
2023-02-12 18:20 ` Conor Dooley
2023-02-12 18:20 ` Conor Dooley
2023-02-12 18:38 ` Guenter Roeck
2023-02-12 18:38 ` Guenter Roeck
2023-02-12 18:38 ` Guenter Roeck
2023-02-12 18:45 ` Conor Dooley
2023-02-12 18:45 ` Conor Dooley
2023-02-12 18:45 ` Conor Dooley
2023-02-12 20:27 ` Guenter Roeck
2023-02-12 20:27 ` Guenter Roeck
2023-02-12 20:27 ` Guenter Roeck
2023-02-12 20:39 ` Conor Dooley
2023-02-12 20:40 ` Conor Dooley
2023-02-12 20:39 ` Conor Dooley
2023-02-12 22:21 ` Guenter Roeck
2023-02-12 22:21 ` Guenter Roeck
2023-02-12 22:21 ` Guenter Roeck
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