From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <rafael@kernel.org>,
<bhelgaas@google.com>, <robert.moore@intel.com>
Subject: Re: [PATCH 07/18] cxl: Add callback to parse the DSLBIS subtable from CDAT
Date: Thu, 9 Feb 2023 13:50:07 +0000 [thread overview]
Message-ID: <20230209135007.0000667d@Huawei.com> (raw)
In-Reply-To: <167571662248.587790.4362747686454305108.stgit@djiang5-mobl3.local>
On Mon, 06 Feb 2023 13:50:23 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Provide a callback to parse the Device Scoped Latency and Bandwidth
> Information Structure (DSLBIS) in the CDAT structures. The DSLBIS
> contains the bandwidth and latency information that's tied to a DSMAS
> handle. The driver will retrieve the read and write latency and
> bandwidth associated with the DSMAS which is tied to a DPA range.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
A few comments inline,
Thanks,
Jonathan
> ---
> drivers/cxl/core/cdat.c | 34 ++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 2 ++
> drivers/cxl/port.c | 9 ++++++++-
> include/acpi/actbl1.h | 5 +++++
> 4 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index f9a64a0f1ee4..3c8f3956487e 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -121,3 +121,37 @@ int cxl_dsmas_parse_entry(struct acpi_cdat_header *header, void *arg)
> return 0;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_dsmas_parse_entry, CXL);
> +
> +int cxl_dslbis_parse_entry(struct acpi_cdat_header *header, void *arg)
> +{
> + struct cxl_port *port = (struct cxl_port *)arg;
> + struct dsmas_entry *dent;
> + struct acpi_cdat_dslbis *dslbis;
Perhaps reorder to maintain the pretty upside-down Christmas trees
(I don't care :)
> + u64 val;
> +
> + if (header->type != ACPI_CDAT_TYPE_DSLBIS)
> + return -EINVAL;
Isn't this guaranteed by the caller? Seems overkill do it twice
and I don't think these will ever be called outside of that wrapper that
loops over the entries. I could be wrong though!
> +
> + dslbis = (struct acpi_cdat_dslbis *)((unsigned long)header + sizeof(*header));
header + 1
> + if ((dslbis->flags & ACPI_CEDT_DSLBIS_MEM_MASK) !=
This field 'must be ignored' if the DSMAS handle isn't a match
(as it's an initiator only entry) Odd though it may seem I think we
might see one of those on a type 3 device and we are probably going to
have other users of this function anyway.
I think you need to do the walk below to check we have a DSMAS match, before
running this check.
> + ACPI_CEDT_DSLBIS_MEM_MEMORY)
> + return 0;
> +
> + if (dslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH)
> + return -ENXIO;
This would probably imply a new HMAT spec value, so probably just
log it and ignore rather than error out.
> +
> + /* Value calculation with base_unit, see ACPI Spec 6.5 5.2.28.4 */
> + val = dslbis->entry[0] * dslbis->entry_base_unit;
In theory this might overflow as u64 * u16.
Doubt it will ever happen in reality, but maybe a check and debug print if it does?
> +
> + mutex_lock(&port->cdat.dsmas_lock);
> + list_for_each_entry(dent, &port->cdat.dsmas_list, list) {
> + if (dslbis->handle == dent->handle) {
> + dent->qos[dslbis->data_type] = val;
> + break;
> + }
> + }
> + mutex_unlock(&port->cdat.dsmas_lock);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dslbis_parse_entry, CXL);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 1e5e69f08480..849b22236f1d 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -705,6 +705,7 @@ struct dsmas_entry {
> struct list_head list;
> struct range dpa_range;
> u16 handle;
> + u64 qos[ACPI_HMAT_WRITE_BANDWIDTH + 1];
> };
>
> typedef int (*cdat_tbl_entry_handler)(struct acpi_cdat_header *header, void *arg);
> @@ -716,6 +717,7 @@ int cdat_table_parse_dslbis(void *table, cdat_tbl_entry_handler handler,
> void *arg);
>
> int cxl_dsmas_parse_entry(struct acpi_cdat_header *header, void *arg);
> +int cxl_dslbis_parse_entry(struct acpi_cdat_header *header, void *arg);
>
> /*
> * Unit test builds overrides this to __weak, find the 'strong' version
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index b1da73e99bab..8de311208b37 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -65,8 +65,15 @@ static int cxl_port_probe(struct device *dev)
> rc = cdat_table_parse_dsmas(port->cdat.table,
> cxl_dsmas_parse_entry,
> (void *)port);
> - if (rc < 0)
> + if (rc > 0) {
> + rc = cdat_table_parse_dslbis(port->cdat.table,
> + cxl_dslbis_parse_entry,
> + (void *)port);
> + if (rc <= 0)
> + dev_dbg(dev, "Failed to parse DSLBIS: %d\n", rc);
If we have entries and they won't parse, I think we should be screaming louder.
dev_warn() would be my preference for this and the one in the previous patch.
Sure we can carry on, but something on the device is not working as expected.
> + } else {
> dev_dbg(dev, "Failed to parse DSMAS: %d\n", rc);
> + }
> }
>
> rc = cxl_hdm_decode_init(cxlds, cxlhdm);
> diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
> index e8297cefde09..ff6092e45196 100644
> --- a/include/acpi/actbl1.h
> +++ b/include/acpi/actbl1.h
> @@ -369,6 +369,11 @@ struct acpi_cdat_dslbis {
> u16 reserved2;
> };
>
> +/* Flags for subtable above */
> +
> +#define ACPI_CEDT_DSLBIS_MEM_MASK GENMASK(3, 0)
> +#define ACPI_CEDT_DSLBIS_MEM_MEMORY 0
> +
> /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */
>
> struct acpi_cdat_dsmscis {
>
>
next prev parent reply other threads:[~2023-02-09 13:50 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:49 [PATCH 00/18] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-02-06 20:49 ` [PATCH 01/18] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-02-09 11:15 ` Jonathan Cameron
2023-02-09 17:28 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 02/18] ACPICA: Export acpi_ut_verify_cdat_checksum() Dave Jiang
2023-02-07 14:19 ` Rafael J. Wysocki
2023-02-07 15:47 ` Dave Jiang
2023-02-09 11:30 ` Jonathan Cameron
2023-02-06 20:49 ` [PATCH 03/18] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-02-09 11:34 ` Jonathan Cameron
2023-02-09 17:31 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 04/18] cxl: Add common helpers for cdat parsing Dave Jiang
2023-02-09 11:58 ` Jonathan Cameron
2023-02-09 22:57 ` Dave Jiang
2023-02-11 10:18 ` Lukas Wunner
2023-02-14 13:17 ` Jonathan Cameron
2023-02-14 20:36 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 05/18] ACPICA: Fix 'struct acpi_cdat_dsmas' spelling mistake Dave Jiang
2023-02-06 22:00 ` Lukas Wunner
2023-02-06 20:50 ` [PATCH 06/18] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-02-09 13:29 ` Jonathan Cameron
2023-02-13 22:55 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 07/18] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-02-09 13:50 ` Jonathan Cameron [this message]
2023-02-14 0:24 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 08/18] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-02-09 14:02 ` Jonathan Cameron
2023-02-14 21:07 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 09/18] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-02-09 14:10 ` Jonathan Cameron
2023-02-14 21:29 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 10/18] PCI: Export pcie_get_speed() using the code from sysfs PCI link speed show function Dave Jiang
2023-02-06 22:27 ` Lukas Wunner
2023-02-07 20:29 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 11/18] PCI: Export pcie_get_width() using the code from sysfs PCI link width " Dave Jiang
2023-02-06 22:43 ` Bjorn Helgaas
2023-02-07 20:35 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 12/18] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-02-06 22:39 ` Bjorn Helgaas
2023-02-07 20:51 ` Dave Jiang
2023-02-08 22:15 ` Bjorn Helgaas
2023-02-08 23:56 ` Dave Jiang
2023-02-09 15:10 ` Jonathan Cameron
2023-02-14 22:22 ` Dave Jiang
2023-02-15 12:13 ` Jonathan Cameron
2023-02-22 17:54 ` Dave Jiang
2023-02-09 15:16 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 13/18] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-02-09 15:24 ` Jonathan Cameron
2023-02-14 23:03 ` Dave Jiang
2023-02-15 13:17 ` Jonathan Cameron
2023-02-15 16:38 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 14/18] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 15/18] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 16/18] cxl: Move reading of CDAT data from device to after media is ready Dave Jiang
2023-02-06 22:17 ` Lukas Wunner
2023-02-07 20:55 ` Dave Jiang
2023-02-09 15:31 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 17/18] cxl: Attach QTG IDs to the DPA ranges for the device Dave Jiang
2023-02-09 15:34 ` Jonathan Cameron
2023-02-06 20:52 ` [PATCH 18/18] cxl: Export sysfs attributes for device QTG IDs Dave Jiang
2023-02-09 15:41 ` Jonathan Cameron
2023-03-23 23:20 ` Dan Williams
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