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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liweiwei@iscas.ac.cn,
	zhiwei_liu@linux.alibaba.com,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v5 2/9] target/riscv: introduce riscv_cpu_cfg()
Date: Thu, 16 Feb 2023 13:21:19 -0300	[thread overview]
Message-ID: <20230216162126.809482-3-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230216162126.809482-1-dbarboza@ventanamicro.com>

We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 target/riscv/cpu.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 01803a020d..368a522b5b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -653,6 +653,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 #endif
 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
+static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env)
+{
+    return env_archcpu(env)->cfg;
+}
+
 #if defined(TARGET_RISCV32)
 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 #else
-- 
2.39.1



  parent reply	other threads:[~2023-02-16 16:21 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-16 16:21 [PATCH v5 0/9] make write_misa a no-op and FEATURE_* cleanups Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 1/9] target/riscv: turn write_misa() into an official no-op Daniel Henrique Barboza
2023-02-16 16:21 ` Daniel Henrique Barboza [this message]
2023-02-16 19:12   ` [PATCH v5 2/9] target/riscv: introduce riscv_cpu_cfg() Richard Henderson
2023-02-16 16:21 ` [PATCH v5 3/9] target/riscv: remove RISCV_FEATURE_DEBUG Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 4/9] target/riscv/cpu.c: error out if EPMP is enabled without PMP Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 5/9] target/riscv: remove RISCV_FEATURE_EPMP Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 6/9] target/riscv: remove RISCV_FEATURE_PMP Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 7/9] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 8/9] target/riscv: remove RISCV_FEATURE_MMU Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 9/9] target/riscv/cpu: remove CPUArchState::features and friends Daniel Henrique Barboza

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