From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v5 7/9] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()
Date: Thu, 16 Feb 2023 13:21:24 -0300 [thread overview]
Message-ID: <20230216162126.809482-8-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230216162126.809482-1-dbarboza@ventanamicro.com>
Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
riscv_isa_string().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
hw/riscv/virt.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..49f2c157f7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+ RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
+
cpu_phandle = (*phandle)++;
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
- if (riscv_feature(&s->soc[socket].harts[cpu].env,
- RISCV_FEATURE_MMU)) {
+ if (cpu_ptr->cfg.mmu) {
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
} else {
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
"riscv,none");
}
- name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+ name = riscv_isa_string(cpu_ptr);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
--
2.39.1
next prev parent reply other threads:[~2023-02-16 16:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 16:21 [PATCH v5 0/9] make write_misa a no-op and FEATURE_* cleanups Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 1/9] target/riscv: turn write_misa() into an official no-op Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 2/9] target/riscv: introduce riscv_cpu_cfg() Daniel Henrique Barboza
2023-02-16 19:12 ` Richard Henderson
2023-02-16 16:21 ` [PATCH v5 3/9] target/riscv: remove RISCV_FEATURE_DEBUG Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 4/9] target/riscv/cpu.c: error out if EPMP is enabled without PMP Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 5/9] target/riscv: remove RISCV_FEATURE_EPMP Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 6/9] target/riscv: remove RISCV_FEATURE_PMP Daniel Henrique Barboza
2023-02-16 16:21 ` Daniel Henrique Barboza [this message]
2023-02-16 16:21 ` [PATCH v5 8/9] target/riscv: remove RISCV_FEATURE_MMU Daniel Henrique Barboza
2023-02-16 16:21 ` [PATCH v5 9/9] target/riscv/cpu: remove CPUArchState::features and friends Daniel Henrique Barboza
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