[PATCH v6 0/4] riscv: Add support for Zicbo[m,z,p] instructions

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

Hi,

This new version contains a change in patch 2 based on Richard's
feedback in v5 [1].

Changes from v5:
- patch 2:
  - check if 'mem' is mapped into RAM with 'tlb_vaddr_to_host' before
    zeroing it.
- v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04414.html

[1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04414.html

Christoph Muellner (4):
  accel/tcg: Add probe_access_range_flags interface
  target/riscv: implement Zicboz extension
  target/riscv: implement Zicbom extension
  target/riscv: add Zicbop cbo.prefetch{i,r,m} placeholder

 accel/tcg/cputlb.c                          |  19 +++
 accel/tcg/user-exec.c                       |  15 +-
 include/exec/exec-all.h                     |  24 +++
 target/riscv/cpu.c                          |   7 +
 target/riscv/cpu.h                          |   4 +
 target/riscv/helper.h                       |   5 +
 target/riscv/insn32.decode                  |  16 +-
 target/riscv/insn_trans/trans_rvzicbo.c.inc |  57 +++++++
 target/riscv/op_helper.c                    | 162 ++++++++++++++++++++
 target/riscv/translate.c                    |   1 +
 10 files changed, 306 insertions(+), 4 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc

-- 
2.39.2