From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com,
richard.henderson@linaro.org,
Christoph Muellner <cmuellner@linux.com>
Subject: [PATCH v6 1/4] accel/tcg: Add probe_access_range_flags interface
Date: Fri, 17 Feb 2023 17:34:42 -0300 [thread overview]
Message-ID: <20230217203445.51077-2-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230217203445.51077-1-dbarboza@ventanamicro.com>
From: Christoph Muellner <cmuellner@linux.com>
The existing probe_access* functions do not allow to specify the
access size and a non-faulting behavior at the same time.
This is resolved by adding a generalization of probe_access_flags()
that takes an additional size parameter.
The semantics is basically the same as probe_access_flags(),
but instead of assuming an access to any byte of the addressed
page, we can restrict to access to a specific area, like
probe_access() allows.
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
---
accel/tcg/cputlb.c | 19 +++++++++++++++++++
accel/tcg/user-exec.c | 15 ++++++++++++---
include/exec/exec-all.h | 24 ++++++++++++++++++++++++
3 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 4812d83961..dd3bc7a356 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1606,6 +1606,25 @@ int probe_access_full(CPUArchState *env, target_ulong addr,
return flags;
}
+int probe_access_range_flags(CPUArchState *env, target_ulong addr,
+ int size, MMUAccessType access_type,
+ int mmu_idx, bool nonfault, void **phost,
+ uintptr_t retaddr)
+{
+ CPUTLBEntryFull *full;
+ int flags = probe_access_internal(env, addr, size, access_type,
+ mmu_idx, nonfault, phost, &full,
+ retaddr);
+
+ /* Handle clean RAM pages. */
+ if (unlikely(flags & TLB_NOTDIRTY)) {
+ notdirty_write(env_cpu(env), addr, 1, full, retaddr);
+ flags &= ~TLB_NOTDIRTY;
+ }
+
+ return flags;
+}
+
int probe_access_flags(CPUArchState *env, target_ulong addr,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t retaddr)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index ae67d84638..a73c840655 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -761,9 +761,10 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra);
}
-int probe_access_flags(CPUArchState *env, target_ulong addr,
- MMUAccessType access_type, int mmu_idx,
- bool nonfault, void **phost, uintptr_t ra)
+int probe_access_range_flags(CPUArchState *env, target_ulong addr,
+ int size, MMUAccessType access_type,
+ int mmu_idx, bool nonfault, void **phost,
+ uintptr_t ra)
{
int flags;
@@ -772,6 +773,14 @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
return flags;
}
+int probe_access_flags(CPUArchState *env, target_ulong addr,
+ MMUAccessType access_type, int mmu_idx,
+ bool nonfault, void **phost, uintptr_t ra)
+{
+ return probe_access_range_flags(env, addr, 0, access_type, mmu_idx,
+ nonfault, phost, ra);
+}
+
void *probe_access(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t ra)
{
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 54585a9954..b75f15f247 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -442,6 +442,30 @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
}
+/**
+ * probe_access_range_flags:
+ * @env: CPUArchState
+ * @addr: guest virtual address to look up
+ * @size: size of the access
+ * @access_type: read, write or execute permission
+ * @mmu_idx: MMU index to use for lookup
+ * @nonfault: suppress the fault
+ * @phost: return value for host address
+ * @retaddr: return address for unwinding
+ *
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
+ * the access range, and storing the host address for RAM in @phost.
+ *
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
+ * Do handle clean pages, so exclude TLB_NOTDIRTY from the returned flags.
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
+ */
+int probe_access_range_flags(CPUArchState *env, target_ulong addr,
+ int size, MMUAccessType access_type,
+ int mmu_idx, bool nonfault, void **phost,
+ uintptr_t retaddr);
+
/**
* probe_access_flags:
* @env: CPUArchState
--
2.39.2
next prev parent reply other threads:[~2023-02-17 20:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 20:34 [PATCH v6 0/4] riscv: Add support for Zicbo[m,z,p] instructions Daniel Henrique Barboza
2023-02-17 20:34 ` Daniel Henrique Barboza [this message]
2023-02-17 20:34 ` [PATCH v6 2/4] target/riscv: implement Zicboz extension Daniel Henrique Barboza
2023-02-18 3:44 ` Richard Henderson
2023-02-18 9:28 ` Daniel Henrique Barboza
2023-02-18 19:35 ` Richard Henderson
2023-02-22 9:37 ` Daniel Henrique Barboza
2023-02-22 17:59 ` Richard Henderson
2023-02-18 13:20 ` weiwei
2023-02-17 20:34 ` [PATCH v6 3/4] target/riscv: implement Zicbom extension Daniel Henrique Barboza
2023-02-18 3:46 ` Richard Henderson
2023-02-17 20:34 ` [PATCH v6 4/4] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder Daniel Henrique Barboza
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