From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v6 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size
Date: Fri, 24 Feb 2023 17:26:30 +0100 [thread overview]
Message-ID: <20230224162631.405473-8-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com>
We're about to allow guests to use the Zicboz extension. KVM
userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 92af6f3f057c..c1a1bb0fa91c 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -52,6 +52,7 @@ struct kvm_riscv_config {
unsigned long mvendorid;
unsigned long marchid;
unsigned long mimpid;
+ unsigned long zicboz_block_size;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7c08567097f0..e5126cefbc87 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -276,6 +276,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
return -EINVAL;
reg_val = riscv_cbom_block_size;
break;
+ case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+ if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
+ return -EINVAL;
+ reg_val = riscv_cboz_block_size;
+ break;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
reg_val = vcpu->arch.mvendorid;
break;
@@ -347,6 +352,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
return -EOPNOTSUPP;
+ case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+ return -EOPNOTSUPP;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
if (!vcpu->arch.ran_atleast_once)
vcpu->arch.mvendorid = reg_val;
--
2.39.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
devicetree@vger.kernel.org
Cc: 'Conor Dooley ' <conor.dooley@microchip.com>,
'Paul Walmsley ' <paul.walmsley@sifive.com>,
'Palmer Dabbelt ' <palmer@dabbelt.com>,
'Sudip Mukherjee ' <sudip.mukherjee@codethink.co.uk>,
'Ben Dooks ' <ben.dooks@codethink.co.uk>,
'Atish Patra ' <atishp@rivosinc.com>,
'Albert Ou ' <aou@eecs.berkeley.edu>,
'Anup Patel ' <apatel@ventanamicro.com>,
'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>,
'Rob Herring ' <robh@kernel.org>,
'Jisheng Zhang ' <jszhang@kernel.org>,
'Heiko Stuebner ' <heiko@sntech.de>,
Anup Patel <anup@brainfault.org>
Subject: [PATCH v6 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size
Date: Fri, 24 Feb 2023 17:26:30 +0100 [thread overview]
Message-ID: <20230224162631.405473-8-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com>
We're about to allow guests to use the Zicboz extension. KVM
userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 92af6f3f057c..c1a1bb0fa91c 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -52,6 +52,7 @@ struct kvm_riscv_config {
unsigned long mvendorid;
unsigned long marchid;
unsigned long mimpid;
+ unsigned long zicboz_block_size;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7c08567097f0..e5126cefbc87 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -276,6 +276,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
return -EINVAL;
reg_val = riscv_cbom_block_size;
break;
+ case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+ if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
+ return -EINVAL;
+ reg_val = riscv_cboz_block_size;
+ break;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
reg_val = vcpu->arch.mvendorid;
break;
@@ -347,6 +352,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
return -EOPNOTSUPP;
+ case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+ return -EOPNOTSUPP;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
if (!vcpu->arch.ran_atleast_once)
vcpu->arch.mvendorid = reg_val;
--
2.39.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
devicetree@vger.kernel.org
Cc: 'Conor Dooley ' <conor.dooley@microchip.com>,
'Paul Walmsley ' <paul.walmsley@sifive.com>,
'Palmer Dabbelt ' <palmer@dabbelt.com>,
'Sudip Mukherjee ' <sudip.mukherjee@codethink.co.uk>,
'Ben Dooks ' <ben.dooks@codethink.co.uk>,
'Atish Patra ' <atishp@rivosinc.com>,
'Albert Ou ' <aou@eecs.berkeley.edu>,
'Anup Patel ' <apatel@ventanamicro.com>,
'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>,
'Rob Herring ' <robh@kernel.org>,
'Jisheng Zhang ' <jszhang@kernel.org>,
'Heiko Stuebner ' <heiko@sntech.de>,
Anup Patel <anup@brainfault.org>
Subject: [PATCH v6 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size
Date: Fri, 24 Feb 2023 17:26:30 +0100 [thread overview]
Message-ID: <20230224162631.405473-8-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com>
We're about to allow guests to use the Zicboz extension. KVM
userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 92af6f3f057c..c1a1bb0fa91c 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -52,6 +52,7 @@ struct kvm_riscv_config {
unsigned long mvendorid;
unsigned long marchid;
unsigned long mimpid;
+ unsigned long zicboz_block_size;
};
/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7c08567097f0..e5126cefbc87 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -276,6 +276,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
return -EINVAL;
reg_val = riscv_cbom_block_size;
break;
+ case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+ if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
+ return -EINVAL;
+ reg_val = riscv_cboz_block_size;
+ break;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
reg_val = vcpu->arch.mvendorid;
break;
@@ -347,6 +352,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
return -EOPNOTSUPP;
+ case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
+ return -EOPNOTSUPP;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
if (!vcpu->arch.ran_atleast_once)
vcpu->arch.mvendorid = reg_val;
--
2.39.1
next prev parent reply other threads:[~2023-02-24 16:26 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 16:26 [PATCH v6 0/8] RISC-V: Apply Zicboz to clear_page Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 1/8] RISC-V: alternatives: Support patching multiple insns in assembly Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 2/8] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 3/8] dt-bindings: riscv: Document cboz-block-size Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 4/8] RISC-V: Add Zicboz detection and block size parsing Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 5/8] RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 6/8] RISC-V: Use Zicboz in clear_page when available Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones [this message]
2023-02-24 16:26 ` [PATCH v6 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` [PATCH v6 8/8] RISC-V: KVM: Expose Zicboz to the guest Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-02-24 16:26 ` Andrew Jones
2023-03-15 4:38 ` Palmer Dabbelt
2023-03-15 4:38 ` Palmer Dabbelt
2023-03-15 4:38 ` Palmer Dabbelt
2023-03-15 4:54 ` Anup Patel
2023-03-15 4:54 ` Anup Patel
2023-03-15 4:54 ` Anup Patel
2023-03-15 4:35 ` [PATCH v6 0/8] RISC-V: Apply Zicboz to clear_page Palmer Dabbelt
2023-03-15 4:35 ` Palmer Dabbelt
2023-03-15 4:35 ` Palmer Dabbelt
2023-03-15 8:53 ` Andrew Jones
2023-03-15 8:53 ` Andrew Jones
2023-03-15 8:53 ` Andrew Jones
2023-03-18 1:00 ` patchwork-bot+linux-riscv
2023-03-18 1:00 ` patchwork-bot+linux-riscv
2023-03-18 1:00 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230224162631.405473-8-ajones@ventanamicro.com \
--to=ajones@ventanamicro.com \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.