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From: Rob Herring <robh@kernel.org>
To: Elad Nachman <enachman@marvell.com>
Cc: thomas.petazzoni@bootlin.com, bhelgaas@google.com,
	lpieralisi@kernel.org, kw@linux.com,
	krzysztof.kozlowski+dt@linaro.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits
Date: Mon, 27 Feb 2023 12:55:57 -0600	[thread overview]
Message-ID: <20230227185557.GA672128-robh@kernel.org> (raw)
In-Reply-To: <20230223180531.15148-5-enachman@marvell.com>

On Thu, Feb 23, 2023 at 08:05:28PM +0200, Elad Nachman wrote:
> From: Elad Nachman <enachman@marvell.com>
> 
> Add properties to support configurable DMA mask bits
> and region mask bits.
> configurable DMA mask bits is needed for Marvell AC5/AC5X SOCs which
> have their physical DDR memory start at address 0x2_0000_0000.
> Configurable region mask bits is needed for the Marvell Armada
> 7020/7040/8040 SOCs when the DT file places the PCIe window above the
> 4GB region.
> The Synopsis Designware PCIe IP in these SOCs is too old to specify the
> highest memory location supported by the PCIe, but practically supports
> such locations. Allow these locations to be specified in the DT file.
> First DT property is called num-dmamask,
> and can range between 33 and 64.
> Second DT property is called num-regionmask,
> and can range between 33 and 64.
> 
> Signed-off-by: Elad Nachman <enachman@marvell.com>
> ---
>  .../devicetree/bindings/pci/snps,dw-pcie-common.yaml   | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index d87e13496834..a1b06ff19ca7 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -261,6 +261,16 @@ properties:
>  
>    dma-coherent: true
>  
> +  num-dmamask:

Nope! There's already a defined way to define DMA/bus addresses and 
sizes in DT. That's dma-ranges.

Rob

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Elad Nachman <enachman@marvell.com>
Cc: thomas.petazzoni@bootlin.com, bhelgaas@google.com,
	lpieralisi@kernel.org, kw@linux.com,
	krzysztof.kozlowski+dt@linaro.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits
Date: Mon, 27 Feb 2023 12:55:57 -0600	[thread overview]
Message-ID: <20230227185557.GA672128-robh@kernel.org> (raw)
In-Reply-To: <20230223180531.15148-5-enachman@marvell.com>

On Thu, Feb 23, 2023 at 08:05:28PM +0200, Elad Nachman wrote:
> From: Elad Nachman <enachman@marvell.com>
> 
> Add properties to support configurable DMA mask bits
> and region mask bits.
> configurable DMA mask bits is needed for Marvell AC5/AC5X SOCs which
> have their physical DDR memory start at address 0x2_0000_0000.
> Configurable region mask bits is needed for the Marvell Armada
> 7020/7040/8040 SOCs when the DT file places the PCIe window above the
> 4GB region.
> The Synopsis Designware PCIe IP in these SOCs is too old to specify the
> highest memory location supported by the PCIe, but practically supports
> such locations. Allow these locations to be specified in the DT file.
> First DT property is called num-dmamask,
> and can range between 33 and 64.
> Second DT property is called num-regionmask,
> and can range between 33 and 64.
> 
> Signed-off-by: Elad Nachman <enachman@marvell.com>
> ---
>  .../devicetree/bindings/pci/snps,dw-pcie-common.yaml   | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index d87e13496834..a1b06ff19ca7 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -261,6 +261,16 @@ properties:
>  
>    dma-coherent: true
>  
> +  num-dmamask:

Nope! There's already a defined way to define DMA/bus addresses and 
sizes in DT. That's dma-ranges.

Rob

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  parent reply	other threads:[~2023-02-27 18:56 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-23 18:05 [PATCH v3 0/7] PCI: dwc: Add support for Marvell AC5 SoC Elad Nachman
2023-02-23 18:05 ` [PATCH v3 1/7] dt-bindings: PCI: armada8k: Add compatible string for " Elad Nachman
2023-02-23 18:05 ` [PATCH v3 2/7] PCI: armada8k: Add AC5 SoC support Elad Nachman
2023-02-23 18:05 ` [PATCH v3 3/7] PCI: armada8k: Add MSI support for AC5 SoC Elad Nachman
2023-02-23 18:05 ` [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits Elad Nachman
2023-02-23 18:12   ` Krzysztof Kozlowski
2023-02-23 18:12     ` Krzysztof Kozlowski
2023-02-27 18:55   ` Rob Herring [this message]
2023-02-27 18:55     ` Rob Herring
2023-02-23 18:05 ` [PATCH v3 5/7] PCI: dwc: support AC5 Legacy PCIe interrupts Elad Nachman
2023-02-23 19:48   ` Bjorn Helgaas
2023-02-23 19:48     ` Bjorn Helgaas
2023-02-23 18:05 ` [PATCH v3 6/7] PCI: dwc: Introduce Configurable DMA mask Elad Nachman
2023-02-23 18:14   ` Krzysztof Kozlowski
2023-02-23 18:14     ` Krzysztof Kozlowski
2023-02-23 18:05 ` [PATCH v3 7/7] PCI: dwc: Introduce region limit from DT Elad Nachman
2023-02-23 18:16   ` Krzysztof Kozlowski
2023-02-23 18:16     ` Krzysztof Kozlowski
2023-02-23 19:42 ` [PATCH v3 0/7] PCI: dwc: Add support for Marvell AC5 SoC Bjorn Helgaas
2023-02-23 19:42   ` Bjorn Helgaas

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