Re: [Intel-gfx] [PATCH] drm/i915/display: Communicate display power demands to pcode more accurately

[kernel test robot <lkp@intel.com>]

Hi Stanislav,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Stanislav-Lisovskiy/drm-i915-display-Communicate-display-power-demands-to-pcode-more-accurately/20230227-175404
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230227095253.22415-1-stanislav.lisovskiy%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/display: Communicate display power demands to pcode more accurately
config: x86_64-defconfig (https://download.01.org/0day-ci/archive/20230227/202302272028.pPiIBz9V-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
        # https://github.com/intel-lab-lkp/linux/commit/bc4de3b25bbf043f68ef862c45f975b79af938be
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Stanislav-Lisovskiy/drm-i915-display-Communicate-display-power-demands-to-pcode-more-accurately/20230227-175404
        git checkout bc4de3b25bbf043f68ef862c45f975b79af938be
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        make W=1 O=build_dir ARCH=x86_64 olddefconfig
        make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302272028.pPiIBz9V-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_cdclk.c:3006:6: error: no previous prototype for 'intel_cdclk_need_serialize' [-Werror=missing-prototypes]
    3006 | bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: all warnings being treated as errors


vim +/intel_cdclk_need_serialize +3006 drivers/gpu/drm/i915/display/intel_cdclk.c

  3005	
> 3006	bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
  3007					const struct intel_cdclk_state *old_cdclk_state,
  3008					const struct intel_cdclk_state *new_cdclk_state)
  3009	{
  3010		/*
  3011		 * We need to poke hw for gen >= 12, because we notify PCode if
  3012		 * pipe power well count changes.
  3013		 */
  3014		return intel_cdclk_changed(&old_cdclk_state->actual,
  3015					   &new_cdclk_state->actual) ||
  3016		       ((DISPLAY_VER(i915) >= 12 &&
  3017			 hweight8(old_cdclk_state->active_pipes) !=
  3018			 hweight8(new_cdclk_state->active_pipes)));
  3019	}
  3020	

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