* [RFC 0/1] ITS fails to allocate on rk3588
@ 2023-02-27 15:18 ` Lucas Tanure
0 siblings, 0 replies; 16+ messages in thread
From: Lucas Tanure @ 2023-02-27 15:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel,
Lucas Tanure, kernel
I am assisting with PCIe and networking bring-up for Rock Pi 5B (RK3588).
This chip uses the same GICv3 as RK356X but has fixed the previous
limitation of GIC only supporting 32-bit addresses.
But the implementation decision for shareability in GICR and GITS is
still the same.
I read the previous thread about this topic:
https://lore.kernel.org/lkml/2791594e-db60-e1d0-88e5-7e5bbd98ae4d@rock-chips.com/T/#m5dbc70ff308d81e98dd0d797e23d3fbf9c353245
From my understanding, the errata numbers Marc Zyngier is referring to
are found in Arm errata documents at developer.arm.com/documentation.
But I could not find Cavium or Broadcom pages for errata with those
numbers in Documentation/arm64/silicon-errata.rst
I could not find an errata document about this shareability issue,
and by what Kever said in the previous thread this could be a
RockChip design decision.
Marc, as I could only find ARM errata numbers, is the errata number
you were expecting generated by ARM only, or RockChip should issue
a document like Arm to detail the issue?
Can this shareability issue be seen as a quirk without an
errata number?
The following patch is based on the work of Peter Geis for the
Quartz64 board and the previous thread feedback.
Lucas Tanure (1):
irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
Documentation/arm64/silicon-errata.rst | 4 +++
arch/arm64/Kconfig | 13 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
--
2.39.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 0/1] ITS fails to allocate on rk3588
@ 2023-02-27 15:18 ` Lucas Tanure
0 siblings, 0 replies; 16+ messages in thread
From: Lucas Tanure @ 2023-02-27 15:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel,
Lucas Tanure, kernel
I am assisting with PCIe and networking bring-up for Rock Pi 5B (RK3588).
This chip uses the same GICv3 as RK356X but has fixed the previous
limitation of GIC only supporting 32-bit addresses.
But the implementation decision for shareability in GICR and GITS is
still the same.
I read the previous thread about this topic:
https://lore.kernel.org/lkml/2791594e-db60-e1d0-88e5-7e5bbd98ae4d@rock-chips.com/T/#m5dbc70ff308d81e98dd0d797e23d3fbf9c353245
From my understanding, the errata numbers Marc Zyngier is referring to
are found in Arm errata documents at developer.arm.com/documentation.
But I could not find Cavium or Broadcom pages for errata with those
numbers in Documentation/arm64/silicon-errata.rst
I could not find an errata document about this shareability issue,
and by what Kever said in the previous thread this could be a
RockChip design decision.
Marc, as I could only find ARM errata numbers, is the errata number
you were expecting generated by ARM only, or RockChip should issue
a document like Arm to detail the issue?
Can this shareability issue be seen as a quirk without an
errata number?
The following patch is based on the work of Peter Geis for the
Quartz64 board and the previous thread feedback.
Lucas Tanure (1):
irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
Documentation/arm64/silicon-errata.rst | 4 +++
arch/arm64/Kconfig | 13 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
--
2.39.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 0/1] ITS fails to allocate on rk3588
@ 2023-02-27 15:18 ` Lucas Tanure
0 siblings, 0 replies; 16+ messages in thread
From: Lucas Tanure @ 2023-02-27 15:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel,
Lucas Tanure, kernel
I am assisting with PCIe and networking bring-up for Rock Pi 5B (RK3588).
This chip uses the same GICv3 as RK356X but has fixed the previous
limitation of GIC only supporting 32-bit addresses.
But the implementation decision for shareability in GICR and GITS is
still the same.
I read the previous thread about this topic:
https://lore.kernel.org/lkml/2791594e-db60-e1d0-88e5-7e5bbd98ae4d@rock-chips.com/T/#m5dbc70ff308d81e98dd0d797e23d3fbf9c353245
From my understanding, the errata numbers Marc Zyngier is referring to
are found in Arm errata documents at developer.arm.com/documentation.
But I could not find Cavium or Broadcom pages for errata with those
numbers in Documentation/arm64/silicon-errata.rst
I could not find an errata document about this shareability issue,
and by what Kever said in the previous thread this could be a
RockChip design decision.
Marc, as I could only find ARM errata numbers, is the errata number
you were expecting generated by ARM only, or RockChip should issue
a document like Arm to detail the issue?
Can this shareability issue be seen as a quirk without an
errata number?
The following patch is based on the work of Peter Geis for the
Quartz64 board and the previous thread feedback.
Lucas Tanure (1):
irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
Documentation/arm64/silicon-errata.rst | 4 +++
arch/arm64/Kconfig | 13 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
2023-02-27 15:18 ` Lucas Tanure
(?)
@ 2023-02-27 15:18 ` Lucas Tanure
-1 siblings, 0 replies; 16+ messages in thread
From: Lucas Tanure @ 2023-02-27 15:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel,
Lucas Tanure, kernel
The GIC600 integration in RK356x, used in rk3588, doesn't support
any of the shareability or cacheability attributes, and requires
both values to be set to 0b00 for all the ITS and Redistributor
tables.
Based on work of Peter Geis for the Quartz64 board.
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
---
Documentation/arm64/silicon-errata.rst | 4 +++
arch/arm64/Kconfig | 13 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index ec5f889d7681..b26cf8ca7d5c 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -209,3 +209,7 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+
+
++----------------+-----------------+-----------------+-----------------------------+
+| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 27b2592698b0..ad3f1742052b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
If unsure, say Y.
+config ROCKCHIP_NO_SHARE
+ bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
+ default y
+ help
+ The GIC600 integration in RK356x doesn't support any of the shareability or
+ cacheability attributes, and requires both values to be set to 0b00 for all
+ the ITS and Redistributor tables.
+
+ Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
+ register reads at GICR and GITS.
+
+ If unsure, say Y.
+
config SOCIONEXT_SYNQUACER_PREITS
bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
default y
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 586271b8aa39..637e2e2a1ab1 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -42,6 +42,7 @@
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
+#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
@@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
its_write_baser(its, baser, val);
tmp = baser->val;
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ else
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+ }
+#endif
+
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*
* Shareability didn't stick. Just use
@@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
{
void __iomem *rbase = gic_data_rdist_rd_base();
struct page *pend_page;
+ struct its_node *its;
phys_addr_t paddr;
u64 val, tmp;
@@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ its = list_first_entry(&its_nodes, struct its_node, entry);
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+#endif
+
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
/*
@@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+#endif
+
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
* The HW reports non-shareable, we must remove the
@@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
return true;
}
+static bool __maybe_unused its_enable_quirk_rk356x(void *data)
+{
+ struct its_node *its = data;
+
+ its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
+ return true;
+}
+
static const struct gic_quirk its_quirks[] = {
#ifdef CONFIG_CAVIUM_ERRATUM_22375
{
@@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
.mask = 0xffffffff,
.init = its_enable_quirk_hip07_161600802,
},
+#endif
+#ifdef CONFIG_ROCKCHIP_NO_SHARE
+ {
+ .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
+ .iidr = 0x0201743b,
+ .mask = 0xffffffff,
+ .init = its_enable_quirk_rk356x,
+ },
#endif
{
}
@@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
gits_write_cbaser(baser, its->base + GITS_CBASER);
tmp = gits_read_cbaser(its->base + GITS_CBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+#endif
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
@ 2023-02-27 15:18 ` Lucas Tanure
0 siblings, 0 replies; 16+ messages in thread
From: Lucas Tanure @ 2023-02-27 15:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel,
Lucas Tanure, kernel
The GIC600 integration in RK356x, used in rk3588, doesn't support
any of the shareability or cacheability attributes, and requires
both values to be set to 0b00 for all the ITS and Redistributor
tables.
Based on work of Peter Geis for the Quartz64 board.
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
---
Documentation/arm64/silicon-errata.rst | 4 +++
arch/arm64/Kconfig | 13 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index ec5f889d7681..b26cf8ca7d5c 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -209,3 +209,7 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+
+
++----------------+-----------------+-----------------+-----------------------------+
+| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 27b2592698b0..ad3f1742052b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
If unsure, say Y.
+config ROCKCHIP_NO_SHARE
+ bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
+ default y
+ help
+ The GIC600 integration in RK356x doesn't support any of the shareability or
+ cacheability attributes, and requires both values to be set to 0b00 for all
+ the ITS and Redistributor tables.
+
+ Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
+ register reads at GICR and GITS.
+
+ If unsure, say Y.
+
config SOCIONEXT_SYNQUACER_PREITS
bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
default y
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 586271b8aa39..637e2e2a1ab1 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -42,6 +42,7 @@
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
+#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
@@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
its_write_baser(its, baser, val);
tmp = baser->val;
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ else
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+ }
+#endif
+
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*
* Shareability didn't stick. Just use
@@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
{
void __iomem *rbase = gic_data_rdist_rd_base();
struct page *pend_page;
+ struct its_node *its;
phys_addr_t paddr;
u64 val, tmp;
@@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ its = list_first_entry(&its_nodes, struct its_node, entry);
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+#endif
+
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
/*
@@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+#endif
+
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
* The HW reports non-shareable, we must remove the
@@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
return true;
}
+static bool __maybe_unused its_enable_quirk_rk356x(void *data)
+{
+ struct its_node *its = data;
+
+ its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
+ return true;
+}
+
static const struct gic_quirk its_quirks[] = {
#ifdef CONFIG_CAVIUM_ERRATUM_22375
{
@@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
.mask = 0xffffffff,
.init = its_enable_quirk_hip07_161600802,
},
+#endif
+#ifdef CONFIG_ROCKCHIP_NO_SHARE
+ {
+ .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
+ .iidr = 0x0201743b,
+ .mask = 0xffffffff,
+ .init = its_enable_quirk_rk356x,
+ },
#endif
{
}
@@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
gits_write_cbaser(baser, its->base + GITS_CBASER);
tmp = gits_read_cbaser(its->base + GITS_CBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+#endif
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
/*
--
2.39.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
@ 2023-02-27 15:18 ` Lucas Tanure
0 siblings, 0 replies; 16+ messages in thread
From: Lucas Tanure @ 2023-02-27 15:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel,
Lucas Tanure, kernel
The GIC600 integration in RK356x, used in rk3588, doesn't support
any of the shareability or cacheability attributes, and requires
both values to be set to 0b00 for all the ITS and Redistributor
tables.
Based on work of Peter Geis for the Quartz64 board.
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
---
Documentation/arm64/silicon-errata.rst | 4 +++
arch/arm64/Kconfig | 13 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index ec5f889d7681..b26cf8ca7d5c 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -209,3 +209,7 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+
+
++----------------+-----------------+-----------------+-----------------------------+
+| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 27b2592698b0..ad3f1742052b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
If unsure, say Y.
+config ROCKCHIP_NO_SHARE
+ bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
+ default y
+ help
+ The GIC600 integration in RK356x doesn't support any of the shareability or
+ cacheability attributes, and requires both values to be set to 0b00 for all
+ the ITS and Redistributor tables.
+
+ Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
+ register reads at GICR and GITS.
+
+ If unsure, say Y.
+
config SOCIONEXT_SYNQUACER_PREITS
bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
default y
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 586271b8aa39..637e2e2a1ab1 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -42,6 +42,7 @@
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
+#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
@@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
its_write_baser(its, baser, val);
tmp = baser->val;
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ else
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+ }
+#endif
+
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*
* Shareability didn't stick. Just use
@@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
{
void __iomem *rbase = gic_data_rdist_rd_base();
struct page *pend_page;
+ struct its_node *its;
phys_addr_t paddr;
u64 val, tmp;
@@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ its = list_first_entry(&its_nodes, struct its_node, entry);
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+#endif
+
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
/*
@@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+#endif
+
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
* The HW reports non-shareable, we must remove the
@@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
return true;
}
+static bool __maybe_unused its_enable_quirk_rk356x(void *data)
+{
+ struct its_node *its = data;
+
+ its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
+ return true;
+}
+
static const struct gic_quirk its_quirks[] = {
#ifdef CONFIG_CAVIUM_ERRATUM_22375
{
@@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
.mask = 0xffffffff,
.init = its_enable_quirk_hip07_161600802,
},
+#endif
+#ifdef CONFIG_ROCKCHIP_NO_SHARE
+ {
+ .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
+ .iidr = 0x0201743b,
+ .mask = 0xffffffff,
+ .init = its_enable_quirk_rk356x,
+ },
#endif
{
}
@@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
gits_write_cbaser(baser, its->base + GITS_CBASER);
tmp = gits_read_cbaser(its->base + GITS_CBASER);
+#if CONFIG_ROCKCHIP_NO_SHARE
+ if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+#endif
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
/*
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [RFC 0/1] ITS fails to allocate on rk3588
2023-02-27 15:18 ` Lucas Tanure
(?)
@ 2023-02-27 21:22 ` Peter Geis
-1 siblings, 0 replies; 16+ messages in thread
From: Peter Geis @ 2023-02-27 21:22 UTC (permalink / raw)
To: Lucas Tanure
Cc: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Kever Yang, linux-rockchip, linux-arm-kernel,
linux-doc, linux-kernel, kernel
On Mon, Feb 27, 2023 at 10:18 AM Lucas Tanure
<lucas.tanure@collabora.com> wrote:
>
> I am assisting with PCIe and networking bring-up for Rock Pi 5B (RK3588).
> This chip uses the same GICv3 as RK356X but has fixed the previous
> limitation of GIC only supporting 32-bit addresses.
>
> But the implementation decision for shareability in GICR and GITS is
> still the same.
>
> I read the previous thread about this topic:
> https://lore.kernel.org/lkml/2791594e-db60-e1d0-88e5-7e5bbd98ae4d@rock-chips.com/T/#m5dbc70ff308d81e98dd0d797e23d3fbf9c353245
>
> From my understanding, the errata numbers Marc Zyngier is referring to
> are found in Arm errata documents at developer.arm.com/documentation.
> But I could not find Cavium or Broadcom pages for errata with those
> numbers in Documentation/arm64/silicon-errata.rst
>
> I could not find an errata document about this shareability issue,
> and by what Kever said in the previous thread this could be a
> RockChip design decision.
>
> Marc, as I could only find ARM errata numbers, is the errata number
> you were expecting generated by ARM only, or RockChip should issue
> a document like Arm to detail the issue?
>
> Can this shareability issue be seen as a quirk without an
> errata number?
>
> The following patch is based on the work of Peter Geis for the
> Quartz64 board and the previous thread feedback.
I see you have included rk356x in this as well. This will only work on
rk356x boards that do not exceed 4GB of ram as the on chip devices are
only 32bit addressable and the kernel by default allocates this in
highmem.
Very Respectfully,
Peter Geis
>
> Lucas Tanure (1):
> irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
>
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 0/1] ITS fails to allocate on rk3588
@ 2023-02-27 21:22 ` Peter Geis
0 siblings, 0 replies; 16+ messages in thread
From: Peter Geis @ 2023-02-27 21:22 UTC (permalink / raw)
To: Lucas Tanure
Cc: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Kever Yang, linux-rockchip, linux-arm-kernel,
linux-doc, linux-kernel, kernel
On Mon, Feb 27, 2023 at 10:18 AM Lucas Tanure
<lucas.tanure@collabora.com> wrote:
>
> I am assisting with PCIe and networking bring-up for Rock Pi 5B (RK3588).
> This chip uses the same GICv3 as RK356X but has fixed the previous
> limitation of GIC only supporting 32-bit addresses.
>
> But the implementation decision for shareability in GICR and GITS is
> still the same.
>
> I read the previous thread about this topic:
> https://lore.kernel.org/lkml/2791594e-db60-e1d0-88e5-7e5bbd98ae4d@rock-chips.com/T/#m5dbc70ff308d81e98dd0d797e23d3fbf9c353245
>
> From my understanding, the errata numbers Marc Zyngier is referring to
> are found in Arm errata documents at developer.arm.com/documentation.
> But I could not find Cavium or Broadcom pages for errata with those
> numbers in Documentation/arm64/silicon-errata.rst
>
> I could not find an errata document about this shareability issue,
> and by what Kever said in the previous thread this could be a
> RockChip design decision.
>
> Marc, as I could only find ARM errata numbers, is the errata number
> you were expecting generated by ARM only, or RockChip should issue
> a document like Arm to detail the issue?
>
> Can this shareability issue be seen as a quirk without an
> errata number?
>
> The following patch is based on the work of Peter Geis for the
> Quartz64 board and the previous thread feedback.
I see you have included rk356x in this as well. This will only work on
rk356x boards that do not exceed 4GB of ram as the on chip devices are
only 32bit addressable and the kernel by default allocates this in
highmem.
Very Respectfully,
Peter Geis
>
> Lucas Tanure (1):
> irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
>
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> --
> 2.39.2
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 0/1] ITS fails to allocate on rk3588
@ 2023-02-27 21:22 ` Peter Geis
0 siblings, 0 replies; 16+ messages in thread
From: Peter Geis @ 2023-02-27 21:22 UTC (permalink / raw)
To: Lucas Tanure
Cc: Catalin Marinas, Will Deacon, Jonathan Corbet, Thomas Gleixner,
Marc Zyngier, Kever Yang, linux-rockchip, linux-arm-kernel,
linux-doc, linux-kernel, kernel
On Mon, Feb 27, 2023 at 10:18 AM Lucas Tanure
<lucas.tanure@collabora.com> wrote:
>
> I am assisting with PCIe and networking bring-up for Rock Pi 5B (RK3588).
> This chip uses the same GICv3 as RK356X but has fixed the previous
> limitation of GIC only supporting 32-bit addresses.
>
> But the implementation decision for shareability in GICR and GITS is
> still the same.
>
> I read the previous thread about this topic:
> https://lore.kernel.org/lkml/2791594e-db60-e1d0-88e5-7e5bbd98ae4d@rock-chips.com/T/#m5dbc70ff308d81e98dd0d797e23d3fbf9c353245
>
> From my understanding, the errata numbers Marc Zyngier is referring to
> are found in Arm errata documents at developer.arm.com/documentation.
> But I could not find Cavium or Broadcom pages for errata with those
> numbers in Documentation/arm64/silicon-errata.rst
>
> I could not find an errata document about this shareability issue,
> and by what Kever said in the previous thread this could be a
> RockChip design decision.
>
> Marc, as I could only find ARM errata numbers, is the errata number
> you were expecting generated by ARM only, or RockChip should issue
> a document like Arm to detail the issue?
>
> Can this shareability issue be seen as a quirk without an
> errata number?
>
> The following patch is based on the work of Peter Geis for the
> Quartz64 board and the previous thread feedback.
I see you have included rk356x in this as well. This will only work on
rk356x boards that do not exceed 4GB of ram as the on chip devices are
only 32bit addressable and the kernel by default allocates this in
highmem.
Very Respectfully,
Peter Geis
>
> Lucas Tanure (1):
> irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
>
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> --
> 2.39.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
2023-02-27 15:18 ` Lucas Tanure
(?)
(?)
@ 2023-02-28 4:21 ` kernel test robot
-1 siblings, 0 replies; 16+ messages in thread
From: kernel test robot @ 2023-02-28 4:21 UTC (permalink / raw)
To: Lucas Tanure; +Cc: oe-kbuild-all
Hi Lucas,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on tip/irq/core soc/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Lucas-Tanure/irqchip-gic-v3-Add-RK3588-GICR-and-GITS-no-share-workaround/20230227-232013
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
patch link: https://lore.kernel.org/r/20230227151847.207922-2-lucas.tanure%40collabora.com
patch subject: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230228/202302281247.ToOTaBnA-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/50d0372c72a4515dd495f751fa7cd299effab96f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Lucas-Tanure/irqchip-gic-v3-Add-RK3588-GICR-and-GITS-no-share-workaround/20230227-232013
git checkout 50d0372c72a4515dd495f751fa7cd299effab96f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/irqchip/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302281247.ToOTaBnA-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/irqchip/irq-gic-v3-its.c: In function 'its_setup_baser':
>> drivers/irqchip/irq-gic-v3-its.c:2363:5: warning: "CONFIG_ROCKCHIP_NO_SHARE" is not defined, evaluates to 0 [-Wundef]
2363 | #if CONFIG_ROCKCHIP_NO_SHARE
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/irqchip/irq-gic-v3-its.c: In function 'its_cpu_init_lpis':
drivers/irqchip/irq-gic-v3-its.c:3110:5: warning: "CONFIG_ROCKCHIP_NO_SHARE" is not defined, evaluates to 0 [-Wundef]
3110 | #if CONFIG_ROCKCHIP_NO_SHARE
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/irqchip/irq-gic-v3-its.c:3140:5: warning: "CONFIG_ROCKCHIP_NO_SHARE" is not defined, evaluates to 0 [-Wundef]
3140 | #if CONFIG_ROCKCHIP_NO_SHARE
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/irqchip/irq-gic-v3-its.c:3070:26: warning: unused variable 'its' [-Wunused-variable]
3070 | struct its_node *its;
| ^~~
drivers/irqchip/irq-gic-v3-its.c: In function 'its_probe_one':
drivers/irqchip/irq-gic-v3-its.c:5136:5: warning: "CONFIG_ROCKCHIP_NO_SHARE" is not defined, evaluates to 0 [-Wundef]
5136 | #if CONFIG_ROCKCHIP_NO_SHARE
| ^~~~~~~~~~~~~~~~~~~~~~~~
vim +/CONFIG_ROCKCHIP_NO_SHARE +2363 drivers/irqchip/irq-gic-v3-its.c
2294
2295 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2296 u64 cache, u64 shr, u32 order, bool indirect)
2297 {
2298 u64 val = its_read_baser(its, baser);
2299 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2300 u64 type = GITS_BASER_TYPE(val);
2301 u64 baser_phys, tmp;
2302 u32 alloc_pages, psz;
2303 struct page *page;
2304 void *base;
2305
2306 psz = baser->psz;
2307 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2308 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2309 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2310 &its->phys_base, its_base_type_string[type],
2311 alloc_pages, GITS_BASER_PAGES_MAX);
2312 alloc_pages = GITS_BASER_PAGES_MAX;
2313 order = get_order(GITS_BASER_PAGES_MAX * psz);
2314 }
2315
2316 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2317 if (!page)
2318 return -ENOMEM;
2319
2320 base = (void *)page_address(page);
2321 baser_phys = virt_to_phys(base);
2322
2323 /* Check if the physical address of the memory is above 48bits */
2324 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2325
2326 /* 52bit PA is supported only when PageSize=64K */
2327 if (psz != SZ_64K) {
2328 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2329 free_pages((unsigned long)base, order);
2330 return -ENXIO;
2331 }
2332
2333 /* Convert 52bit PA to 48bit field */
2334 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2335 }
2336
2337 retry_baser:
2338 val = (baser_phys |
2339 (type << GITS_BASER_TYPE_SHIFT) |
2340 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2341 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2342 cache |
2343 shr |
2344 GITS_BASER_VALID);
2345
2346 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2347
2348 switch (psz) {
2349 case SZ_4K:
2350 val |= GITS_BASER_PAGE_SIZE_4K;
2351 break;
2352 case SZ_16K:
2353 val |= GITS_BASER_PAGE_SIZE_16K;
2354 break;
2355 case SZ_64K:
2356 val |= GITS_BASER_PAGE_SIZE_64K;
2357 break;
2358 }
2359
2360 its_write_baser(its, baser, val);
2361 tmp = baser->val;
2362
> 2363 #if CONFIG_ROCKCHIP_NO_SHARE
2364 if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
2365 if (tmp & GITS_BASER_SHAREABILITY_MASK)
2366 tmp &= ~GITS_BASER_SHAREABILITY_MASK;
2367 else
2368 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2369 }
2370 #endif
2371
2372 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2373 /*
2374 * Shareability didn't stick. Just use
2375 * whatever the read reported, which is likely
2376 * to be the only thing this redistributor
2377 * supports. If that's zero, make it
2378 * non-cacheable as well.
2379 */
2380 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2381 if (!shr) {
2382 cache = GITS_BASER_nC;
2383 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2384 }
2385 goto retry_baser;
2386 }
2387
2388 if (val != tmp) {
2389 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2390 &its->phys_base, its_base_type_string[type],
2391 val, tmp);
2392 free_pages((unsigned long)base, order);
2393 return -ENXIO;
2394 }
2395
2396 baser->order = order;
2397 baser->base = base;
2398 baser->psz = psz;
2399 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2400
2401 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2402 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2403 its_base_type_string[type],
2404 (unsigned long)virt_to_phys(base),
2405 indirect ? "indirect" : "flat", (int)esz,
2406 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2407
2408 return 0;
2409 }
2410
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
2023-02-27 15:18 ` Lucas Tanure
(?)
@ 2023-02-28 8:35 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-02-28 8:35 UTC (permalink / raw)
To: Lucas Tanure, Catalin Marinas, Will Deacon, Jonathan Corbet,
Thomas Gleixner, Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel, kernel
Il 27/02/23 16:18, Lucas Tanure ha scritto:
> The GIC600 integration in RK356x, used in rk3588, doesn't support
> any of the shareability or cacheability attributes, and requires
> both values to be set to 0b00 for all the ITS and Redistributor
> tables.
>
> Based on work of Peter Geis for the Quartz64 board.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..b26cf8ca7d5c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -209,3 +209,7 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> +
> ++----------------+-----------------+-----------------+-----------------------------+
> +| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
> ++----------------+-----------------+-----------------+-----------------------------+
This should go after Qualcomm, as it looks like this file is ordered by name but
for some reason Fujitsu got at the bottom.
Just keep your new addition ordered.
Besides, I propose the following:
| RockChip | RK3588 | N/A | ROCKCHIP_ITS_ERRATUM |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 27b2592698b0..ad3f1742052b 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>
> If unsure, say Y.
>
> +config ROCKCHIP_NO_SHARE
config ROCKCHIP_ITS_ERRATUM ?? :-)
> + bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
You've got a typo here: GIC6000.
> + default y
> + help
> + The GIC600 integration in RK356x doesn't support any of the shareability or
> + cacheability attributes, and requires both values to be set to 0b00 for all
> + the ITS and Redistributor tables.
> +
> + Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
> + register reads at GICR and GITS.
> +
> + If unsure, say Y.
> +
> config SOCIONEXT_SYNQUACER_PREITS
> bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
> default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..637e2e2a1ab1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,6 +42,7 @@
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
> +#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
>
> #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
> #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
> @@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> its_write_baser(its, baser, val);
> tmp = baser->val;
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
None of the other workarounds have an ifdef in parsing the flags, so I think
that you can avoid enclosing this in a preprocessor `if` block.
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
> + if (tmp & GITS_BASER_SHAREABILITY_MASK)
> + tmp &= ~GITS_BASER_SHAREABILITY_MASK;
> + else
> + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
> + }
> +#endif
> +
> if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
> /*
> * Shareability didn't stick. Just use
> @@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
> {
> void __iomem *rbase = gic_data_rdist_rd_base();
> struct page *pend_page;
> + struct its_node *its;
> phys_addr_t paddr;
> u64 val, tmp;
>
> @@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
> gicr_write_propbaser(val, rbase + GICR_PROPBASER);
> tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
ditto.
> + its = list_first_entry(&its_nodes, struct its_node, entry);
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
> +#endif
> +
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> /*
> @@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
> gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
> tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
> +#endif
> +
> if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
> /*
> * The HW reports non-shareable, we must remove the
> @@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
> return true;
> }
>
> +static bool __maybe_unused its_enable_quirk_rk356x(void *data)
> +{
> + struct its_node *its = data;
> +
> + its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
> + return true;
> +}
> +
> static const struct gic_quirk its_quirks[] = {
> #ifdef CONFIG_CAVIUM_ERRATUM_22375
> {
> @@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
> .mask = 0xffffffff,
> .init = its_enable_quirk_hip07_161600802,
> },
> +#endif
> +#ifdef CONFIG_ROCKCHIP_NO_SHARE
here it's fine.
> + {
> + .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
> + .iidr = 0x0201743b,
> + .mask = 0xffffffff,
> + .init = its_enable_quirk_rk356x,
> + },
> #endif
> {
> }
> @@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
> gits_write_cbaser(baser, its->base + GITS_CBASER);
> tmp = gits_read_cbaser(its->base + GITS_CBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
...here it's not, again.
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
> +#endif
> if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
> if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> /*
Regards,
Angelo
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
@ 2023-02-28 8:35 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-02-28 8:35 UTC (permalink / raw)
To: Lucas Tanure, Catalin Marinas, Will Deacon, Jonathan Corbet,
Thomas Gleixner, Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel, kernel
Il 27/02/23 16:18, Lucas Tanure ha scritto:
> The GIC600 integration in RK356x, used in rk3588, doesn't support
> any of the shareability or cacheability attributes, and requires
> both values to be set to 0b00 for all the ITS and Redistributor
> tables.
>
> Based on work of Peter Geis for the Quartz64 board.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..b26cf8ca7d5c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -209,3 +209,7 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> +
> ++----------------+-----------------+-----------------+-----------------------------+
> +| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
> ++----------------+-----------------+-----------------+-----------------------------+
This should go after Qualcomm, as it looks like this file is ordered by name but
for some reason Fujitsu got at the bottom.
Just keep your new addition ordered.
Besides, I propose the following:
| RockChip | RK3588 | N/A | ROCKCHIP_ITS_ERRATUM |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 27b2592698b0..ad3f1742052b 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>
> If unsure, say Y.
>
> +config ROCKCHIP_NO_SHARE
config ROCKCHIP_ITS_ERRATUM ?? :-)
> + bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
You've got a typo here: GIC6000.
> + default y
> + help
> + The GIC600 integration in RK356x doesn't support any of the shareability or
> + cacheability attributes, and requires both values to be set to 0b00 for all
> + the ITS and Redistributor tables.
> +
> + Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
> + register reads at GICR and GITS.
> +
> + If unsure, say Y.
> +
> config SOCIONEXT_SYNQUACER_PREITS
> bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
> default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..637e2e2a1ab1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,6 +42,7 @@
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
> +#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
>
> #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
> #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
> @@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> its_write_baser(its, baser, val);
> tmp = baser->val;
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
None of the other workarounds have an ifdef in parsing the flags, so I think
that you can avoid enclosing this in a preprocessor `if` block.
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
> + if (tmp & GITS_BASER_SHAREABILITY_MASK)
> + tmp &= ~GITS_BASER_SHAREABILITY_MASK;
> + else
> + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
> + }
> +#endif
> +
> if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
> /*
> * Shareability didn't stick. Just use
> @@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
> {
> void __iomem *rbase = gic_data_rdist_rd_base();
> struct page *pend_page;
> + struct its_node *its;
> phys_addr_t paddr;
> u64 val, tmp;
>
> @@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
> gicr_write_propbaser(val, rbase + GICR_PROPBASER);
> tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
ditto.
> + its = list_first_entry(&its_nodes, struct its_node, entry);
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
> +#endif
> +
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> /*
> @@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
> gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
> tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
> +#endif
> +
> if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
> /*
> * The HW reports non-shareable, we must remove the
> @@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
> return true;
> }
>
> +static bool __maybe_unused its_enable_quirk_rk356x(void *data)
> +{
> + struct its_node *its = data;
> +
> + its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
> + return true;
> +}
> +
> static const struct gic_quirk its_quirks[] = {
> #ifdef CONFIG_CAVIUM_ERRATUM_22375
> {
> @@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
> .mask = 0xffffffff,
> .init = its_enable_quirk_hip07_161600802,
> },
> +#endif
> +#ifdef CONFIG_ROCKCHIP_NO_SHARE
here it's fine.
> + {
> + .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
> + .iidr = 0x0201743b,
> + .mask = 0xffffffff,
> + .init = its_enable_quirk_rk356x,
> + },
> #endif
> {
> }
> @@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
> gits_write_cbaser(baser, its->base + GITS_CBASER);
> tmp = gits_read_cbaser(its->base + GITS_CBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
...here it's not, again.
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
> +#endif
> if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
> if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> /*
Regards,
Angelo
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
@ 2023-02-28 8:35 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-02-28 8:35 UTC (permalink / raw)
To: Lucas Tanure, Catalin Marinas, Will Deacon, Jonathan Corbet,
Thomas Gleixner, Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel, kernel
Il 27/02/23 16:18, Lucas Tanure ha scritto:
> The GIC600 integration in RK356x, used in rk3588, doesn't support
> any of the shareability or cacheability attributes, and requires
> both values to be set to 0b00 for all the ITS and Redistributor
> tables.
>
> Based on work of Peter Geis for the Quartz64 board.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..b26cf8ca7d5c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -209,3 +209,7 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> +
> ++----------------+-----------------+-----------------+-----------------------------+
> +| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
> ++----------------+-----------------+-----------------+-----------------------------+
This should go after Qualcomm, as it looks like this file is ordered by name but
for some reason Fujitsu got at the bottom.
Just keep your new addition ordered.
Besides, I propose the following:
| RockChip | RK3588 | N/A | ROCKCHIP_ITS_ERRATUM |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 27b2592698b0..ad3f1742052b 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>
> If unsure, say Y.
>
> +config ROCKCHIP_NO_SHARE
config ROCKCHIP_ITS_ERRATUM ?? :-)
> + bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
You've got a typo here: GIC6000.
> + default y
> + help
> + The GIC600 integration in RK356x doesn't support any of the shareability or
> + cacheability attributes, and requires both values to be set to 0b00 for all
> + the ITS and Redistributor tables.
> +
> + Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
> + register reads at GICR and GITS.
> +
> + If unsure, say Y.
> +
> config SOCIONEXT_SYNQUACER_PREITS
> bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
> default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..637e2e2a1ab1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,6 +42,7 @@
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
> +#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
>
> #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
> #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
> @@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> its_write_baser(its, baser, val);
> tmp = baser->val;
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
None of the other workarounds have an ifdef in parsing the flags, so I think
that you can avoid enclosing this in a preprocessor `if` block.
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
> + if (tmp & GITS_BASER_SHAREABILITY_MASK)
> + tmp &= ~GITS_BASER_SHAREABILITY_MASK;
> + else
> + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
> + }
> +#endif
> +
> if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
> /*
> * Shareability didn't stick. Just use
> @@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
> {
> void __iomem *rbase = gic_data_rdist_rd_base();
> struct page *pend_page;
> + struct its_node *its;
> phys_addr_t paddr;
> u64 val, tmp;
>
> @@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
> gicr_write_propbaser(val, rbase + GICR_PROPBASER);
> tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
ditto.
> + its = list_first_entry(&its_nodes, struct its_node, entry);
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
> +#endif
> +
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> /*
> @@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
> gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
> tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
> +#endif
> +
> if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
> /*
> * The HW reports non-shareable, we must remove the
> @@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
> return true;
> }
>
> +static bool __maybe_unused its_enable_quirk_rk356x(void *data)
> +{
> + struct its_node *its = data;
> +
> + its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
> + return true;
> +}
> +
> static const struct gic_quirk its_quirks[] = {
> #ifdef CONFIG_CAVIUM_ERRATUM_22375
> {
> @@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
> .mask = 0xffffffff,
> .init = its_enable_quirk_hip07_161600802,
> },
> +#endif
> +#ifdef CONFIG_ROCKCHIP_NO_SHARE
here it's fine.
> + {
> + .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
> + .iidr = 0x0201743b,
> + .mask = 0xffffffff,
> + .init = its_enable_quirk_rk356x,
> + },
> #endif
> {
> }
> @@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
> gits_write_cbaser(baser, its->base + GITS_CBASER);
> tmp = gits_read_cbaser(its->base + GITS_CBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
...here it's not, again.
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
> +#endif
> if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
> if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> /*
Regards,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
2023-02-27 15:18 ` Lucas Tanure
(?)
@ 2023-02-28 17:21 ` Robin Murphy
-1 siblings, 0 replies; 16+ messages in thread
From: Robin Murphy @ 2023-02-28 17:21 UTC (permalink / raw)
To: Lucas Tanure, Catalin Marinas, Will Deacon, Jonathan Corbet,
Thomas Gleixner, Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel, kernel
On 27/02/2023 3:18 pm, Lucas Tanure wrote:
> The GIC600 integration in RK356x, used in rk3588, doesn't support
> any of the shareability or cacheability attributes, and requires
> both values to be set to 0b00 for all the ITS and Redistributor
> tables.
>
> Based on work of Peter Geis for the Quartz64 board.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..b26cf8ca7d5c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -209,3 +209,7 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> +
> ++----------------+-----------------+-----------------+-----------------------------+
> +| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 27b2592698b0..ad3f1742052b 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>
> If unsure, say Y.
>
> +config ROCKCHIP_NO_SHARE
> + bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
> + default y
> + help
> + The GIC600 integration in RK356x doesn't support any of the shareability or
> + cacheability attributes, and requires both values to be set to 0b00 for all
> + the ITS and Redistributor tables.
> +
> + Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
> + register reads at GICR and GITS.
> +
> + If unsure, say Y.
> +
> config SOCIONEXT_SYNQUACER_PREITS
> bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
> default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..637e2e2a1ab1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,6 +42,7 @@
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
> +#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
>
> #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
> #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
> @@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> its_write_baser(its, baser, val);
> tmp = baser->val;
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
> + if (tmp & GITS_BASER_SHAREABILITY_MASK)
> + tmp &= ~GITS_BASER_SHAREABILITY_MASK;
> + else
> + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
> + }
> +#endif
> +
> if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
> /*
> * Shareability didn't stick. Just use
> @@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
> {
> void __iomem *rbase = gic_data_rdist_rd_base();
> struct page *pend_page;
> + struct its_node *its;
> phys_addr_t paddr;
> u64 val, tmp;
>
> @@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
> gicr_write_propbaser(val, rbase + GICR_PROPBASER);
> tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + its = list_first_entry(&its_nodes, struct its_node, entry);
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
> +#endif
> +
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> /*
> @@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
> gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
> tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
> +#endif
> +
> if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
> /*
> * The HW reports non-shareable, we must remove the
> @@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
> return true;
> }
>
> +static bool __maybe_unused its_enable_quirk_rk356x(void *data)
> +{
> + struct its_node *its = data;
> +
> + its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
> + return true;
> +}
> +
> static const struct gic_quirk its_quirks[] = {
> #ifdef CONFIG_CAVIUM_ERRATUM_22375
> {
> @@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
> .mask = 0xffffffff,
> .init = its_enable_quirk_hip07_161600802,
> },
> +#endif
> +#ifdef CONFIG_ROCKCHIP_NO_SHARE
> + {
> + .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
> + .iidr = 0x0201743b,
This represents the Arm Ltd. GIC-600 implementation. It is definitely
not Rockchip-specific, and applying this quirk to the likes of Ampere
Altra or AWS Graviton2 would be extremely unpopular.
TBH I think this whole thing would be reasonable to handle in a generic
manner using the now-standard "dma-noncoherent" property to override the
driver's expectations. Given the apparent lack of clear integration
guidelines it's only likely to continue happening.
Thanks,
Robin.
> + .mask = 0xffffffff,
> + .init = its_enable_quirk_rk356x,
> + },
> #endif
> {
> }
> @@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
> gits_write_cbaser(baser, its->base + GITS_CBASER);
> tmp = gits_read_cbaser(its->base + GITS_CBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
> +#endif
> if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
> if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> /*
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
@ 2023-02-28 17:21 ` Robin Murphy
0 siblings, 0 replies; 16+ messages in thread
From: Robin Murphy @ 2023-02-28 17:21 UTC (permalink / raw)
To: Lucas Tanure, Catalin Marinas, Will Deacon, Jonathan Corbet,
Thomas Gleixner, Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel, kernel
On 27/02/2023 3:18 pm, Lucas Tanure wrote:
> The GIC600 integration in RK356x, used in rk3588, doesn't support
> any of the shareability or cacheability attributes, and requires
> both values to be set to 0b00 for all the ITS and Redistributor
> tables.
>
> Based on work of Peter Geis for the Quartz64 board.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..b26cf8ca7d5c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -209,3 +209,7 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> +
> ++----------------+-----------------+-----------------+-----------------------------+
> +| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 27b2592698b0..ad3f1742052b 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>
> If unsure, say Y.
>
> +config ROCKCHIP_NO_SHARE
> + bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
> + default y
> + help
> + The GIC600 integration in RK356x doesn't support any of the shareability or
> + cacheability attributes, and requires both values to be set to 0b00 for all
> + the ITS and Redistributor tables.
> +
> + Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
> + register reads at GICR and GITS.
> +
> + If unsure, say Y.
> +
> config SOCIONEXT_SYNQUACER_PREITS
> bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
> default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..637e2e2a1ab1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,6 +42,7 @@
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
> +#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
>
> #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
> #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
> @@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> its_write_baser(its, baser, val);
> tmp = baser->val;
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
> + if (tmp & GITS_BASER_SHAREABILITY_MASK)
> + tmp &= ~GITS_BASER_SHAREABILITY_MASK;
> + else
> + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
> + }
> +#endif
> +
> if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
> /*
> * Shareability didn't stick. Just use
> @@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
> {
> void __iomem *rbase = gic_data_rdist_rd_base();
> struct page *pend_page;
> + struct its_node *its;
> phys_addr_t paddr;
> u64 val, tmp;
>
> @@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
> gicr_write_propbaser(val, rbase + GICR_PROPBASER);
> tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + its = list_first_entry(&its_nodes, struct its_node, entry);
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
> +#endif
> +
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> /*
> @@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
> gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
> tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
> +#endif
> +
> if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
> /*
> * The HW reports non-shareable, we must remove the
> @@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
> return true;
> }
>
> +static bool __maybe_unused its_enable_quirk_rk356x(void *data)
> +{
> + struct its_node *its = data;
> +
> + its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
> + return true;
> +}
> +
> static const struct gic_quirk its_quirks[] = {
> #ifdef CONFIG_CAVIUM_ERRATUM_22375
> {
> @@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
> .mask = 0xffffffff,
> .init = its_enable_quirk_hip07_161600802,
> },
> +#endif
> +#ifdef CONFIG_ROCKCHIP_NO_SHARE
> + {
> + .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
> + .iidr = 0x0201743b,
This represents the Arm Ltd. GIC-600 implementation. It is definitely
not Rockchip-specific, and applying this quirk to the likes of Ampere
Altra or AWS Graviton2 would be extremely unpopular.
TBH I think this whole thing would be reasonable to handle in a generic
manner using the now-standard "dma-noncoherent" property to override the
driver's expectations. Given the apparent lack of clear integration
guidelines it's only likely to continue happening.
Thanks,
Robin.
> + .mask = 0xffffffff,
> + .init = its_enable_quirk_rk356x,
> + },
> #endif
> {
> }
> @@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
> gits_write_cbaser(baser, its->base + GITS_CBASER);
> tmp = gits_read_cbaser(its->base + GITS_CBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
> +#endif
> if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
> if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> /*
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround
@ 2023-02-28 17:21 ` Robin Murphy
0 siblings, 0 replies; 16+ messages in thread
From: Robin Murphy @ 2023-02-28 17:21 UTC (permalink / raw)
To: Lucas Tanure, Catalin Marinas, Will Deacon, Jonathan Corbet,
Thomas Gleixner, Marc Zyngier, Peter Geis, Kever Yang
Cc: linux-rockchip, linux-arm-kernel, linux-doc, linux-kernel, kernel
On 27/02/2023 3:18 pm, Lucas Tanure wrote:
> The GIC600 integration in RK356x, used in rk3588, doesn't support
> any of the shareability or cacheability attributes, and requires
> both values to be set to 0b00 for all the ITS and Redistributor
> tables.
>
> Based on work of Peter Geis for the Quartz64 board.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
> ---
> Documentation/arm64/silicon-errata.rst | 4 +++
> arch/arm64/Kconfig | 13 ++++++++
> drivers/irqchip/irq-gic-v3-its.c | 42 ++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..b26cf8ca7d5c 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -209,3 +209,7 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> +
> ++----------------+-----------------+-----------------+-----------------------------+
> +| RockChip | RK3588 | N/A | ROCKCHIP_NO_SHARE |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 27b2592698b0..ad3f1742052b 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,19 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>
> If unsure, say Y.
>
> +config ROCKCHIP_NO_SHARE
> + bool "Rockchip RK3588 GIC6000 No shareability or cacheability attributes"
> + default y
> + help
> + The GIC600 integration in RK356x doesn't support any of the shareability or
> + cacheability attributes, and requires both values to be set to 0b00 for all
> + the ITS and Redistributor tables.
> +
> + Work around the issue by clearing the GICR_PROPBASER_SHAREABILITY_MASK from
> + register reads at GICR and GITS.
> +
> + If unsure, say Y.
> +
> config SOCIONEXT_SYNQUACER_PREITS
> bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
> default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..637e2e2a1ab1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,6 +42,7 @@
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
> #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
> +#define ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE (1ULL << 3)
>
> #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
> #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
> @@ -2359,6 +2360,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> its_write_baser(its, baser, val);
> tmp = baser->val;
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE) {
> + if (tmp & GITS_BASER_SHAREABILITY_MASK)
> + tmp &= ~GITS_BASER_SHAREABILITY_MASK;
> + else
> + gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
> + }
> +#endif
> +
> if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
> /*
> * Shareability didn't stick. Just use
> @@ -3057,6 +3067,7 @@ static void its_cpu_init_lpis(void)
> {
> void __iomem *rbase = gic_data_rdist_rd_base();
> struct page *pend_page;
> + struct its_node *its;
> phys_addr_t paddr;
> u64 val, tmp;
>
> @@ -3096,6 +3107,12 @@ static void its_cpu_init_lpis(void)
> gicr_write_propbaser(val, rbase + GICR_PROPBASER);
> tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + its = list_first_entry(&its_nodes, struct its_node, entry);
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
> +#endif
> +
> if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
> if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
> /*
> @@ -3120,6 +3137,11 @@ static void its_cpu_init_lpis(void)
> gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
> tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
> +#endif
> +
> if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
> /*
> * The HW reports non-shareable, we must remove the
> @@ -4710,6 +4732,14 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
> return true;
> }
>
> +static bool __maybe_unused its_enable_quirk_rk356x(void *data)
> +{
> + struct its_node *its = data;
> +
> + its->flags |= ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE;
> + return true;
> +}
> +
> static const struct gic_quirk its_quirks[] = {
> #ifdef CONFIG_CAVIUM_ERRATUM_22375
> {
> @@ -4755,6 +4785,14 @@ static const struct gic_quirk its_quirks[] = {
> .mask = 0xffffffff,
> .init = its_enable_quirk_hip07_161600802,
> },
> +#endif
> +#ifdef CONFIG_ROCKCHIP_NO_SHARE
> + {
> + .desc = "ITS: Rockchip RK356X/RK3588 doesn't support shareability",
> + .iidr = 0x0201743b,
This represents the Arm Ltd. GIC-600 implementation. It is definitely
not Rockchip-specific, and applying this quirk to the likes of Ampere
Altra or AWS Graviton2 would be extremely unpopular.
TBH I think this whole thing would be reasonable to handle in a generic
manner using the now-standard "dma-noncoherent" property to override the
driver's expectations. Given the apparent lack of clear integration
guidelines it's only likely to continue happening.
Thanks,
Robin.
> + .mask = 0xffffffff,
> + .init = its_enable_quirk_rk356x,
> + },
> #endif
> {
> }
> @@ -5096,6 +5134,10 @@ static int __init its_probe_one(struct resource *res,
> gits_write_cbaser(baser, its->base + GITS_CBASER);
> tmp = gits_read_cbaser(its->base + GITS_CBASER);
>
> +#if CONFIG_ROCKCHIP_NO_SHARE
> + if (its->flags & ITS_FLAGS_WORKAROUND_ROCKCHIP_NOSHARE)
> + tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
> +#endif
> if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
> if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> /*
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-02-28 17:23 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-27 15:18 [RFC 0/1] ITS fails to allocate on rk3588 Lucas Tanure
2023-02-27 15:18 ` Lucas Tanure
2023-02-27 15:18 ` Lucas Tanure
2023-02-27 15:18 ` [RFC 1/1] irqchip/gic-v3: Add RK3588 GICR and GITS no share workaround Lucas Tanure
2023-02-27 15:18 ` Lucas Tanure
2023-02-27 15:18 ` Lucas Tanure
2023-02-28 4:21 ` kernel test robot
2023-02-28 8:35 ` AngeloGioacchino Del Regno
2023-02-28 8:35 ` AngeloGioacchino Del Regno
2023-02-28 8:35 ` AngeloGioacchino Del Regno
2023-02-28 17:21 ` Robin Murphy
2023-02-28 17:21 ` Robin Murphy
2023-02-28 17:21 ` Robin Murphy
2023-02-27 21:22 ` [RFC 0/1] ITS fails to allocate on rk3588 Peter Geis
2023-02-27 21:22 ` Peter Geis
2023-02-27 21:22 ` Peter Geis
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