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From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Jassi Brar <jassisinghbrar@gmail.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v3 1/8] mailbox: mpfs: fix an incorrect mask width
Date: Tue,  7 Mar 2023 20:22:51 +0000	[thread overview]
Message-ID: <20230307202257.1762151-2-conor@kernel.org> (raw)
In-Reply-To: <20230307202257.1762151-1-conor@kernel.org>

From: Conor Dooley <conor.dooley@microchip.com>

The system controller registers on PolarFire SoC are 32 bits wide, so
16 + 16 as the first input to GENMASK_ULL() gives a 33 bit wide mask.
It probably should have been immediately obvious when it was pointed
out during review that the width required using GENMASK_ULL() - but I
scarcely knew what I was doing at the time and missed it.
The mistake ends up being moot as it is a mask after all, but it is
incorrect and should be fixed.

No functional change intended.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/mailbox/mailbox-mpfs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 853901acaeec..d37560e91116 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -39,7 +39,7 @@
 #define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
 
 #define SCB_CTRL_POS (16)
-#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
+#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH - 1, SCB_CTRL_POS)
 
 /* SCBCTRL service status register */
 
@@ -118,6 +118,7 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
 	}
 
 	opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
+
 	tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
 	tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
 	writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
-- 
2.39.2


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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Jassi Brar <jassisinghbrar@gmail.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v3 1/8] mailbox: mpfs: fix an incorrect mask width
Date: Tue,  7 Mar 2023 20:22:51 +0000	[thread overview]
Message-ID: <20230307202257.1762151-2-conor@kernel.org> (raw)
In-Reply-To: <20230307202257.1762151-1-conor@kernel.org>

From: Conor Dooley <conor.dooley@microchip.com>

The system controller registers on PolarFire SoC are 32 bits wide, so
16 + 16 as the first input to GENMASK_ULL() gives a 33 bit wide mask.
It probably should have been immediately obvious when it was pointed
out during review that the width required using GENMASK_ULL() - but I
scarcely knew what I was doing at the time and missed it.
The mistake ends up being moot as it is a mask after all, but it is
incorrect and should be fixed.

No functional change intended.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/mailbox/mailbox-mpfs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 853901acaeec..d37560e91116 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -39,7 +39,7 @@
 #define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
 
 #define SCB_CTRL_POS (16)
-#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
+#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH - 1, SCB_CTRL_POS)
 
 /* SCBCTRL service status register */
 
@@ -118,6 +118,7 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
 	}
 
 	opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
+
 	tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
 	tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
 	writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
-- 
2.39.2


  reply	other threads:[~2023-03-07 20:23 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-07 20:22 [PATCH v3 0/8] Hey Jassi, all, Conor Dooley
2023-03-07 20:22 ` Conor Dooley
2023-03-07 20:22 ` Conor Dooley [this message]
2023-03-07 20:22   ` [PATCH v3 1/8] mailbox: mpfs: fix an incorrect mask width Conor Dooley
2023-03-07 20:22 ` [PATCH v3 2/8] mailbox: mpfs: switch to txdone_poll Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:22 ` [PATCH v3 3/8] mailbox: mpfs: ditch a useless busy check Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:22 ` [PATCH v3 4/8] mailbox: mpfs: check the service status in .tx_done() Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:22 ` [PATCH v3 5/8] soc: microchip: mpfs: fix some horrible alignment Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:22 ` [PATCH v3 6/8] soc: microchip: mpfs: use a consistent completion timeout Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:22 ` [PATCH v3 7/8] soc: microchip: mpfs: simplify error handling in mpfs_blocking_transaction() Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:22 ` [PATCH v3 8/8] soc: microchip: mpfs: handle timeouts and failed services differently Conor Dooley
2023-03-07 20:22   ` Conor Dooley
2023-03-07 20:30 ` mailbox,soc: mpfs: add support for fallible services (was [PATCH v3 0/8] Hey Jassi, all,) Conor Dooley
2023-03-07 20:30   ` Conor Dooley
2023-03-29 16:15   ` Conor Dooley
2023-03-29 16:15     ` Conor Dooley
2023-03-31 15:03     ` Jassi Brar
2023-03-31 15:03       ` Jassi Brar
2023-03-31 18:14       ` Conor Dooley
2023-03-31 18:14         ` Conor Dooley
2023-04-03 18:11 ` [PATCH v3 0/8] Hey Jassi, all, Valentina.FernandezAlanis
2023-04-03 18:11   ` Valentina.FernandezAlanis
2023-04-03 18:28 ` Conor Dooley
2023-04-03 18:28   ` Conor Dooley

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