From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH for-8.1 01/17] target/riscv/cpu.c: add riscv_cpu_validate_v()
Date: Wed, 8 Mar 2023 17:19:09 -0300 [thread overview]
Message-ID: <20230308201925.258223-2-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com>
The code that validates ext_v in riscv_cpu_validate_set_extensions() is
not properly indented - we're missing an extra indent level right after
the first check that uses cfg->elen.
In the end the 'v' verification is a bit too large in comparison with
the others, and can be put in a separated function to enhance the
readability of riscv_cpu_validate_set_extensions().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 83 ++++++++++++++++++++++++++--------------------
1 file changed, 47 insertions(+), 36 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..5060a98b6d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -802,6 +802,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
+static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+ Error **errp)
+{
+ int vext_version = VEXT_VERSION_1_00_0;
+
+ if (!is_power_of_2(cfg->vlen)) {
+ error_setg(errp, "Vector extension VLEN must be power of 2");
+ return;
+ }
+ if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
+ error_setg(errp,
+ "Vector extension implementation only supports VLEN "
+ "in the range [128, %d]", RV_VLEN_MAX);
+ return;
+ }
+ if (!is_power_of_2(cfg->elen)) {
+ error_setg(errp, "Vector extension ELEN must be power of 2");
+ return;
+ }
+ if (cfg->elen > 64 || cfg->elen < 8) {
+ error_setg(errp,
+ "Vector extension implementation only supports ELEN "
+ "in the range [8, 64]");
+ return;
+ }
+ if (cfg->vext_spec) {
+ if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
+ } else {
+ error_setg(errp, "Unsupported vector spec version '%s'",
+ cfg->vext_spec);
+ return;
+ }
+ } else {
+ qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
+ }
+ set_vext_version(env, vext_version);
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly, doing a set_misa() in the end.
@@ -993,44 +1033,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
ext |= RVH;
}
if (cpu->cfg.ext_v) {
- int vext_version = VEXT_VERSION_1_00_0;
- ext |= RVV;
- if (!is_power_of_2(cpu->cfg.vlen)) {
- error_setg(errp,
- "Vector extension VLEN must be power of 2");
- return;
- }
- if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
- error_setg(errp,
- "Vector extension implementation only supports VLEN "
- "in the range [128, %d]", RV_VLEN_MAX);
- return;
- }
- if (!is_power_of_2(cpu->cfg.elen)) {
- error_setg(errp,
- "Vector extension ELEN must be power of 2");
- return;
- }
- if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
- error_setg(errp,
- "Vector extension implementation only supports ELEN "
- "in the range [8, 64]");
+ Error *local_err = NULL;
+
+ riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
return;
}
- if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
- vext_version = VEXT_VERSION_1_00_0;
- } else {
- error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
- return;
- }
- } else {
- qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
- }
- set_vext_version(env, vext_version);
+
+ ext |= RVV;
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
--
2.39.2
next prev parent reply other threads:[~2023-03-08 20:19 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 20:19 [PATCH for-8.1 00/17] centralize CPU extensions logic Daniel Henrique Barboza
2023-03-08 20:19 ` Daniel Henrique Barboza [this message]
2023-03-08 20:19 ` [PATCH for-8.1 02/17] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-03-09 7:28 ` LIU Zhiwei
2023-03-08 20:19 ` [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-03-09 7:28 ` LIU Zhiwei
2023-03-09 16:22 ` Daniel Henrique Barboza
2023-03-10 0:18 ` Alistair Francis
2023-03-08 20:19 ` [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro Daniel Henrique Barboza
2023-03-08 23:00 ` Richard Henderson
2023-03-09 15:59 ` Daniel Henrique Barboza
2023-03-09 7:31 ` LIU Zhiwei
2023-03-08 20:19 ` [PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec() Daniel Henrique Barboza
2023-03-08 23:06 ` Richard Henderson
2023-03-08 20:19 ` [PATCH for-8.1 06/17] target/riscv: move realize() validations to riscv_cpu_validate_set_extensions() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set Daniel Henrique Barboza
2023-03-09 7:10 ` LIU Zhiwei
2023-03-09 16:23 ` Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 15/17] target/riscv: add RVG Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 17/17] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-03-09 7:27 ` LIU Zhiwei
2023-03-09 7:40 ` LIU Zhiwei
2023-03-09 16:35 ` Daniel Henrique Barboza
2023-03-09 16:33 ` Daniel Henrique Barboza
2023-03-09 21:14 ` [PATCH for-8.1 00/17] centralize CPU extensions logic Daniel Henrique Barboza
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