From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
Date: Wed, 8 Mar 2023 17:19:15 -0300 [thread overview]
Message-ID: <20230308201925.258223-8-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com>
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should always account for them. CPUs such as sifive_e need to
disable settings that aren't enabled simply because the parent class
happens to be enabling it.
Moving all configurations from the parent class to each CPU will
centralize the config of each CPU into its own init(), which is clearer
than having to account to whatever happens to be set in the parent
device. These settings are also being set in register_cpu_props() when
no 'misa_ext' is set, so for these CPUs we don't need changes. Named
CPUs will receive all cfgs that the parent were setting into their
init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 48 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e2cd55320c..499738d2dd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -325,7 +325,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
static void riscv_any_cpu_init(Object *obj)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64)
@@ -340,6 +341,12 @@ static void riscv_any_cpu_init(Object *obj)
env->priv_ver = PRIV_VERSION_LATEST;
register_cpu_props(obj);
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
}
#if defined(TARGET_RISCV64)
@@ -358,13 +365,20 @@ static void rv64_base_cpu_init(Object *obj)
static void rv64_sifive_u_cpu_init(Object *obj)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(obj);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
}
static void rv64_sifive_e_cpu_init(Object *obj)
@@ -375,10 +389,14 @@ static void rv64_sifive_e_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
register_cpu_props(obj);
env->priv_ver = PRIV_VERSION_1_10_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
static void rv64_thead_c906_cpu_init(Object *obj)
@@ -411,6 +429,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.pmp = true;
}
static void rv128_base_cpu_init(Object *obj)
@@ -447,7 +469,8 @@ static void rv32_base_cpu_init(Object *obj)
static void rv32_sifive_u_cpu_init(Object *obj)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(obj);
@@ -455,6 +478,12 @@ static void rv32_sifive_u_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
}
static void rv32_sifive_e_cpu_init(Object *obj)
@@ -465,10 +494,14 @@ static void rv32_sifive_e_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
register_cpu_props(obj);
env->priv_ver = PRIV_VERSION_1_10_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
static void rv32_ibex_cpu_init(Object *obj)
@@ -479,11 +512,15 @@ static void rv32_ibex_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
register_cpu_props(obj);
env->priv_ver = PRIV_VERSION_1_11_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
cpu->cfg.epmp = true;
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
static void rv32_imafcu_nommu_cpu_init(Object *obj)
@@ -494,10 +531,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
register_cpu_props(obj);
env->priv_ver = PRIV_VERSION_1_10_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
#endif
@@ -1357,11 +1398,6 @@ static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
- cpu->cfg.ext_ifencei = true;
- cpu->cfg.ext_icsr = true;
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
--
2.39.2
next prev parent reply other threads:[~2023-03-08 20:19 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 20:19 [PATCH for-8.1 00/17] centralize CPU extensions logic Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 01/17] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 02/17] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-03-09 7:28 ` LIU Zhiwei
2023-03-08 20:19 ` [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-03-09 7:28 ` LIU Zhiwei
2023-03-09 16:22 ` Daniel Henrique Barboza
2023-03-10 0:18 ` Alistair Francis
2023-03-08 20:19 ` [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro Daniel Henrique Barboza
2023-03-08 23:00 ` Richard Henderson
2023-03-09 15:59 ` Daniel Henrique Barboza
2023-03-09 7:31 ` LIU Zhiwei
2023-03-08 20:19 ` [PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec() Daniel Henrique Barboza
2023-03-08 23:06 ` Richard Henderson
2023-03-08 20:19 ` [PATCH for-8.1 06/17] target/riscv: move realize() validations to riscv_cpu_validate_set_extensions() Daniel Henrique Barboza
2023-03-08 20:19 ` Daniel Henrique Barboza [this message]
2023-03-08 20:19 ` [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set Daniel Henrique Barboza
2023-03-09 7:10 ` LIU Zhiwei
2023-03-09 16:23 ` Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 15/17] target/riscv: add RVG Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 17/17] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-03-09 7:27 ` LIU Zhiwei
2023-03-09 7:40 ` LIU Zhiwei
2023-03-09 16:35 ` Daniel Henrique Barboza
2023-03-09 16:33 ` Daniel Henrique Barboza
2023-03-09 21:14 ` [PATCH for-8.1 00/17] centralize CPU extensions logic Daniel Henrique Barboza
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