From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Fan Ni <fan.ni@samsung.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Michael Tsirkin" <mst@redhat.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"linuxarm@huawei.com" <linuxarm@huawei.com>,
"Ira Weiny" <ira.weiny@intel.com>,
"Alison Schofield" <alison.schofield@intel.com>,
"Michael Roth" <michael.roth@amd.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Dave Jiang" <dave.jiang@intel.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Eric Blake" <eblake@redhat.com>,
"Mike Maslenkin" <mike.maslenkin@gmail.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Thomas Huth" <thuth@redhat.com>
Subject: Re: [RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
Date: Tue, 14 Mar 2023 11:53:07 +0000 [thread overview]
Message-ID: <20230314115307.000038d6@Huawei.com> (raw)
In-Reply-To: <20230307192641.GH1489326@bgt-140510-bm03>
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> > FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
> >
> > +typedef struct CXLError {
> > + QTAILQ_ENTRY(CXLError) node;
> > + int type; /* Error code as per FE definition */
> > + uint32_t header[32];
> Instead of using 32 here, would it be better to use
> CXL_RAS_ERR_HEADER_NUM?
Yes, that would be better. Please send a patch.
> > +} CXLError;
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Fan Ni <fan.ni@samsung.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Michael Tsirkin" <mst@redhat.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"linuxarm@huawei.com" <linuxarm@huawei.com>,
"Ira Weiny" <ira.weiny@intel.com>,
"Alison Schofield" <alison.schofield@intel.com>,
"Michael Roth" <michael.roth@amd.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Dave Jiang" <dave.jiang@intel.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Eric Blake" <eblake@redhat.com>,
"Mike Maslenkin" <mike.maslenkin@gmail.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Thomas Huth" <thuth@redhat.com>
Subject: Re: [RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
Date: Tue, 14 Mar 2023 11:53:07 +0000 [thread overview]
Message-ID: <20230314115307.000038d6@Huawei.com> (raw)
In-Reply-To: <20230307192641.GH1489326@bgt-140510-bm03>
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> > FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
> >
> > +typedef struct CXLError {
> > + QTAILQ_ENTRY(CXLError) node;
> > + int type; /* Error code as per FE definition */
> > + uint32_t header[32];
> Instead of using 32 here, would it be better to use
> CXL_RAS_ERR_HEADER_NUM?
Yes, that would be better. Please send a patch.
> > +} CXLError;
next prev parent reply other threads:[~2023-03-14 11:53 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-02 13:37 [RESEND PATCH v6 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-02 13:37 ` [RESEND PATCH v6 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:21 ` Fan Ni
2023-05-02 8:54 ` Michael S. Tsirkin
2023-03-02 13:37 ` [RESEND PATCH v6 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:21 ` Fan Ni
2023-03-02 13:37 ` [RESEND PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:37 ` Fan Ni
2023-03-02 13:37 ` [RESEND PATCH v6 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:51 ` Fan Ni
2023-03-02 13:37 ` [RESEND PATCH v6 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:52 ` Fan Ni
2023-03-02 13:37 ` [RESEND PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:52 ` Fan Ni
2023-03-02 13:37 ` [RESEND PATCH v6 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-06 17:53 ` Fan Ni
2023-03-02 13:37 ` [RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
2023-03-02 13:37 ` Jonathan Cameron via
2023-03-07 17:22 ` Michael S. Tsirkin
2023-03-07 19:26 ` Fan Ni
2023-03-08 1:34 ` Michael S. Tsirkin
2023-03-14 11:53 ` Jonathan Cameron [this message]
2023-03-14 11:53 ` Jonathan Cameron via
2023-03-06 21:57 ` [RESEND PATCH v6 0/8] hw/cxl: RAS error emulation and injection Michael S. Tsirkin
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