[kvm-unit-tests PATCH v4 0/3] s390x: Add misaligned instruction tests

[kvm-unit-tests PATCH v4 0/3] s390x: Add misaligned instruction tests

[Nina Schoetterl-Glausch]

Instructions on s390 must be halfword aligned.
Add two tests for that.
These currently fail when using TCG, Ilya Leoshkevich <iii@linux.ibm.com>
posted fixes to the qemu mailing list.

v3 -> v4:
 * zero whole register with xgr (thanks Janosch)
 * pick up tags (thanks Janosch)

v2 -> v3:
 * pick up R-b (thanks Janosch)
 * use br instead of bcr (thanks Claudio)
 * use text section instead of rodata for ex target (thanks Claudio)
 * fix label position (thanks Claudio)

v1 -> v2:
 * rebase
 * use PSW macros
 * simplify odd psw test (thanks Claudio)
 * rename some identifiers
 * pick up R-b (thanks Claudio)

Nina Schoetterl-Glausch (3):
  s390x/spec_ex: Use PSW macro
  s390x/spec_ex: Add test introducing odd address into PSW
  s390x/spec_ex: Add test of EXECUTE with odd target address

 s390x/spec_ex.c | 85 +++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 76 insertions(+), 9 deletions(-)

Range-diff against v3:
1:  6ae1eb7d = 1:  c00f8aa2 s390x/spec_ex: Use PSW macro
2:  a0d02438 ! 2:  d9e3f6e0 s390x/spec_ex: Add test introducing odd address into PSW
    @@ Commit message
         the odd address.
         Add a test for this.
     
    +    Acked-by: Janosch Frank <frankja@linux.ibm.com>
         Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
     
      ## s390x/spec_ex.c ##
    @@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
     +
     +	expect_invalid_psw(odd);
     +	fixup_psw.mask = extract_psw_mask();
    -+	asm volatile ( "xr	%%r0,%%r0\n"
    ++	asm volatile ( "xgr	%%r0,%%r0\n"
     +		"	larl	%%r1,0f\n"
     +		"	stg	%%r1,%[fixup_addr]\n"
     +		"	lpswe	%[odd_psw]\n"
3:  e771deeb ! 3:  7ea75611 s390x/spec_ex: Add test of EXECUTE with odd target address
    @@ Commit message
         specification exception occurs.
         Add a test for this.
     
    +    Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
         Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
     
      ## s390x/spec_ex.c ##

base-commit: 20de8c3b54078ebc3df0b47344f9ce55bf52b7a5
-- 
2.39.1

[kvm-unit-tests PATCH v4 1/3] s390x/spec_ex: Use PSW macro

[Nina Schoetterl-Glausch]

Replace explicit psw definition by PSW macro.
No functional change intended.

Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
---
 s390x/spec_ex.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
index 42ecaed3..2adc5996 100644
--- a/s390x/spec_ex.c
+++ b/s390x/spec_ex.c
@@ -105,10 +105,7 @@ static int check_invalid_psw(void)
 /* For normal PSWs bit 12 has to be 0 to be a valid PSW*/
 static int psw_bit_12_is_1(void)
 {
-	struct psw invalid = {
-		.mask = BIT(63 - 12),
-		.addr = 0x00000000deadbeee
-	};
+	struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee);
 
 	expect_invalid_psw(invalid);
 	load_psw(invalid);
@@ -118,10 +115,7 @@ static int psw_bit_12_is_1(void)
 /* A short PSW needs to have bit 12 set to be valid. */
 static int short_psw_bit_12_is_0(void)
 {
-	struct psw invalid = {
-		.mask = BIT(63 - 12),
-		.addr = 0x00000000deadbeee
-	};
+	struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee);
 	struct short_psw short_invalid = {
 		.mask = 0x0,
 		.addr = 0xdeadbeee
-- 
2.39.1

[kvm-unit-tests PATCH v4 2/3] s390x/spec_ex: Add test introducing odd address into PSW

[Nina Schoetterl-Glausch]

Instructions on s390 must be halfword aligned.
Introducing an odd instruction address into the PSW leads to a
specification exception when attempting to execute the instruction at
the odd address.
Add a test for this.

Acked-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
---
 s390x/spec_ex.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
index 2adc5996..ab023347 100644
--- a/s390x/spec_ex.c
+++ b/s390x/spec_ex.c
@@ -88,12 +88,23 @@ static void expect_invalid_psw(struct psw psw)
 	invalid_psw_expected = true;
 }
 
+static void clear_invalid_psw(void)
+{
+	expected_psw = PSW(0, 0);
+	invalid_psw_expected = false;
+}
+
 static int check_invalid_psw(void)
 {
 	/* Since the fixup sets this to false we check for false here. */
 	if (!invalid_psw_expected) {
+		/*
+		 * Early exception recognition: pgm_int_id == 0.
+		 * Late exception recognition: psw address has been
+		 *	incremented by pgm_int_id (unpredictable value)
+		 */
 		if (expected_psw.mask == invalid_psw.mask &&
-		    expected_psw.addr == invalid_psw.addr)
+		    expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id)
 			return 0;
 		report_fail("Wrong invalid PSW");
 	} else {
@@ -112,6 +123,42 @@ static int psw_bit_12_is_1(void)
 	return check_invalid_psw();
 }
 
+extern char misaligned_code[];
+asm (  ".balign	2\n"
+"	. = . + 1\n"
+"misaligned_code:\n"
+"	larl	%r0,0\n"
+"	br	%r1\n"
+);
+
+static int psw_odd_address(void)
+{
+	struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code);
+	uint64_t executed_addr;
+
+	expect_invalid_psw(odd);
+	fixup_psw.mask = extract_psw_mask();
+	asm volatile ( "xgr	%%r0,%%r0\n"
+		"	larl	%%r1,0f\n"
+		"	stg	%%r1,%[fixup_addr]\n"
+		"	lpswe	%[odd_psw]\n"
+		"0:	lr	%[executed_addr],%%r0\n"
+	: [fixup_addr] "=&T" (fixup_psw.addr),
+	  [executed_addr] "=d" (executed_addr)
+	: [odd_psw] "Q" (odd)
+	: "cc", "%r0", "%r1"
+	);
+
+	if (!executed_addr) {
+		return check_invalid_psw();
+	} else {
+		assert(executed_addr == odd.addr);
+		clear_invalid_psw();
+		report_fail("did not execute unaligned instructions");
+		return 1;
+	}
+}
+
 /* A short PSW needs to have bit 12 set to be valid. */
 static int short_psw_bit_12_is_0(void)
 {
@@ -170,6 +217,7 @@ struct spec_ex_trigger {
 static const struct spec_ex_trigger spec_ex_triggers[] = {
 	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
 	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
+	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
 	{ "bad_alignment", &bad_alignment, true, NULL },
 	{ "not_even", &not_even, true, NULL },
 	{ NULL, NULL, false, NULL },
-- 
2.39.1

[kvm-unit-tests PATCH v4 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Nina Schoetterl-Glausch]

The EXECUTE instruction executes the instruction at the given target
address. This address must be halfword aligned, otherwise a
specification exception occurs.
Add a test for this.

Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
---
 s390x/spec_ex.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
index ab023347..b4b9095f 100644
--- a/s390x/spec_ex.c
+++ b/s390x/spec_ex.c
@@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
 	return 0;
 }
 
+static int odd_ex_target(void)
+{
+	uint64_t pre_target_addr;
+	int to = 0, from = 0x0dd;
+
+	asm volatile ( ".pushsection .text.ex_odd\n"
+		"	.balign	2\n"
+		"pre_odd_ex_target:\n"
+		"	. = . + 1\n"
+		"	lr	%[to],%[from]\n"
+		"	.popsection\n"
+
+		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
+		"	ex	0,1(%[pre_target_addr])\n"
+		: [pre_target_addr] "=&a" (pre_target_addr),
+		  [to] "+d" (to)
+		: [from] "d" (from)
+	);
+
+	assert((pre_target_addr + 1) & 1);
+	report(to != from, "did not perform ex with odd target");
+	return 0;
+}
+
 static int bad_alignment(void)
 {
 	uint32_t words[5] __attribute__((aligned(16)));
@@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = {
 	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
 	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
 	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
+	{ "odd_ex_target", &odd_ex_target, true, NULL },
 	{ "bad_alignment", &bad_alignment, true, NULL },
 	{ "not_even", &not_even, true, NULL },
 	{ NULL, NULL, false, NULL },
-- 
2.39.1

Re: [kvm-unit-tests PATCH v4 0/3] s390x: Add misaligned instruction tests

[Claudio Imbrenda]

On Fri, 17 Mar 2023 14:32:50 +0100
Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:

> Instructions on s390 must be halfword aligned.
> Add two tests for that.
> These currently fail when using TCG, Ilya Leoshkevich <iii@linux.ibm.com>
> posted fixes to the qemu mailing list.

Whole series:

Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>


> 
> v3 -> v4:
>  * zero whole register with xgr (thanks Janosch)
>  * pick up tags (thanks Janosch)
> 
> v2 -> v3:
>  * pick up R-b (thanks Janosch)
>  * use br instead of bcr (thanks Claudio)
>  * use text section instead of rodata for ex target (thanks Claudio)
>  * fix label position (thanks Claudio)
> 
> v1 -> v2:
>  * rebase
>  * use PSW macros
>  * simplify odd psw test (thanks Claudio)
>  * rename some identifiers
>  * pick up R-b (thanks Claudio)
> 
> Nina Schoetterl-Glausch (3):
>   s390x/spec_ex: Use PSW macro
>   s390x/spec_ex: Add test introducing odd address into PSW
>   s390x/spec_ex: Add test of EXECUTE with odd target address
> 
>  s390x/spec_ex.c | 85 +++++++++++++++++++++++++++++++++++++++++++------
>  1 file changed, 76 insertions(+), 9 deletions(-)
> 
> Range-diff against v3:
> 1:  6ae1eb7d = 1:  c00f8aa2 s390x/spec_ex: Use PSW macro
> 2:  a0d02438 ! 2:  d9e3f6e0 s390x/spec_ex: Add test introducing odd address into PSW
>     @@ Commit message
>          the odd address.
>          Add a test for this.
>      
>     +    Acked-by: Janosch Frank <frankja@linux.ibm.com>
>          Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
>      
>       ## s390x/spec_ex.c ##
>     @@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
>      +
>      +	expect_invalid_psw(odd);
>      +	fixup_psw.mask = extract_psw_mask();
>     -+	asm volatile ( "xr	%%r0,%%r0\n"
>     ++	asm volatile ( "xgr	%%r0,%%r0\n"
>      +		"	larl	%%r1,0f\n"
>      +		"	stg	%%r1,%[fixup_addr]\n"
>      +		"	lpswe	%[odd_psw]\n"
> 3:  e771deeb ! 3:  7ea75611 s390x/spec_ex: Add test of EXECUTE with odd target address
>     @@ Commit message
>          specification exception occurs.
>          Add a test for this.
>      
>     +    Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
>          Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
>      
>       ## s390x/spec_ex.c ##
> 
> base-commit: 20de8c3b54078ebc3df0b47344f9ce55bf52b7a5

Re: [kvm-unit-tests PATCH v4 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Thomas Huth]

On 17/03/2023 14.32, Nina Schoetterl-Glausch wrote:
> The EXECUTE instruction executes the instruction at the given target
> address. This address must be halfword aligned, otherwise a
> specification exception occurs.
> Add a test for this.
> 
> Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
> Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> ---
>   s390x/spec_ex.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
> 
> diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> index ab023347..b4b9095f 100644
> --- a/s390x/spec_ex.c
> +++ b/s390x/spec_ex.c
> @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
>   	return 0;
>   }
>   
> +static int odd_ex_target(void)
> +{
> +	uint64_t pre_target_addr;
> +	int to = 0, from = 0x0dd;
> +
> +	asm volatile ( ".pushsection .text.ex_odd\n"
> +		"	.balign	2\n"
> +		"pre_odd_ex_target:\n"
> +		"	. = . + 1\n"
> +		"	lr	%[to],%[from]\n"
> +		"	.popsection\n"
> +
> +		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
> +		"	ex	0,1(%[pre_target_addr])\n"
> +		: [pre_target_addr] "=&a" (pre_target_addr),
> +		  [to] "+d" (to)
> +		: [from] "d" (from)
> +	);
> +
> +	assert((pre_target_addr + 1) & 1);
> +	report(to != from, "did not perform ex with odd target");
> +	return 0;
> +}

  Hi Nina,

FWIW, this fails to compile with Clang v15 here:

s390x/spec_ex.c:187:4: error: symbol 'pre_odd_ex_target' is already defined
                 "pre_odd_ex_target:\n"
                  ^
<inline asm>:3:1: note: instantiated into assembly here
pre_odd_ex_target:

No clue yet why that happens ... but compiling with Clang seems to be broken 
on some other spots, too, so this is not really critical right now ;-)

  Thomas

Re: [kvm-unit-tests PATCH v4 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Nina Schoetterl-Glausch]

On Mon, 2023-04-03 at 17:38 +0200, Thomas Huth wrote:
> On 17/03/2023 14.32, Nina Schoetterl-Glausch wrote:
> > The EXECUTE instruction executes the instruction at the given target
> > address. This address must be halfword aligned, otherwise a
> > specification exception occurs.
> > Add a test for this.
> > 
> > Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
> > Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> > ---
> >   s390x/spec_ex.c | 25 +++++++++++++++++++++++++
> >   1 file changed, 25 insertions(+)
> > 
> > diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> > index ab023347..b4b9095f 100644
> > --- a/s390x/spec_ex.c
> > +++ b/s390x/spec_ex.c
> > @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
> >   	return 0;
> >   }
> >   
> > +static int odd_ex_target(void)
> > +{
> > +	uint64_t pre_target_addr;
> > +	int to = 0, from = 0x0dd;
> > +
> > +	asm volatile ( ".pushsection .text.ex_odd\n"
> > +		"	.balign	2\n"
> > +		"pre_odd_ex_target:\n"
> > +		"	. = . + 1\n"
> > +		"	lr	%[to],%[from]\n"
> > +		"	.popsection\n"
> > +
> > +		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
> > +		"	ex	0,1(%[pre_target_addr])\n"
> > +		: [pre_target_addr] "=&a" (pre_target_addr),
> > +		  [to] "+d" (to)
> > +		: [from] "d" (from)
> > +	);
> > +
> > +	assert((pre_target_addr + 1) & 1);
> > +	report(to != from, "did not perform ex with odd target");
> > +	return 0;
> > +}
> 
>   Hi Nina,
> 
> FWIW, this fails to compile with Clang v15 here:
> 
> s390x/spec_ex.c:187:4: error: symbol 'pre_odd_ex_target' is already defined
>                  "pre_odd_ex_target:\n"
>                   ^
> <inline asm>:3:1: note: instantiated into assembly here
> pre_odd_ex_target:
> 
> No clue yet why that happens ... but compiling with Clang seems to be broken 
> on some other spots, too, so this is not really critical right now ;-)

Thanks, I guess it inlines the function and emits the asm twice.
Interestingly clang cannot load the address of the misaligned_code symbol in C code due to alignement,
so I had to work around that, too.

> 
>   Thomas
>