From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
richard.henderson@linaro.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 07/19] target/riscv: remove cpu->cfg.ext_f
Date: Mon, 27 Mar 2023 19:49:22 -0300 [thread overview]
Message-ID: <20230327224934.363314-8-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230327224934.363314-1-dbarboza@ventanamicro.com>
Create a new "f" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
replaced with riscv_has_ext(env, RVF).
Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 20 ++++++++++----------
target/riscv/cpu.h | 1 -
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fed697be9d..54e88f2b71 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -813,12 +813,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
riscv_has_ext(env, RVA) &&
- cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
+ riscv_has_ext(env, RVF) &&
+ riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
- cpu->cfg.ext_f = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@@ -855,7 +855,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
+ if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
}
@@ -869,12 +869,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zfhmin = true;
}
- if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
+ if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
}
- if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
+ if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
error_setg(errp, "D extension requires F extension");
return;
}
@@ -899,7 +899,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
+ if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
@@ -932,7 +932,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_setg(errp, "Zfinx extension requires Zicsr");
return;
}
- if (cpu->cfg.ext_f) {
+ if (riscv_has_ext(env, RVF)) {
error_setg(errp,
"Zfinx cannot be supported together with F extension");
return;
@@ -1101,7 +1101,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVA)) {
ext |= RVA;
}
- if (riscv_cpu_cfg(env)->ext_f) {
+ if (riscv_has_ext(env, RVF)) {
ext |= RVF;
}
if (riscv_has_ext(env, RVD)) {
@@ -1441,6 +1441,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVC, .enabled = true},
{.name = "d", .description = "Double-precision float point",
.misa_bit = RVD, .enabled = true},
+ {.name = "f", .description = "Single-precision float point",
+ .misa_bit = RVF, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1467,7 +1469,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
- DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@@ -1578,7 +1579,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
- cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e4cf79e36f..ce23b1c431 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -422,7 +422,6 @@ struct RISCVCPUConfig {
bool ext_e;
bool ext_g;
bool ext_m;
- bool ext_f;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.39.2
next prev parent reply other threads:[~2023-03-27 22:50 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 22:49 [PATCH v2 00/19] remove MISA ext_N flags from cpu->cfg Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 02/19] target/riscv: remove MISA properties from isa_edata_arr[] Daniel Henrique Barboza
2023-03-29 8:32 ` liweiwei
2023-03-29 15:17 ` Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 03/19] target/riscv: introduce riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 04/19] target/riscv: remove cpu->cfg.ext_a Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 05/19] target/riscv: remove cpu->cfg.ext_c Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 06/19] target/riscv: remove cpu->cfg.ext_d Daniel Henrique Barboza
2023-03-27 22:49 ` Daniel Henrique Barboza [this message]
2023-03-27 22:49 ` [PATCH v2 08/19] target/riscv: remove cpu->cfg.ext_i Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 09/19] target/riscv: remove cpu->cfg.ext_e Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 10/19] target/riscv: remove cpu->cfg.ext_m Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 11/19] target/riscv: remove cpu->cfg.ext_s Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 12/19] target/riscv: remove cpu->cfg.ext_u Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg() Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g Daniel Henrique Barboza
2023-03-27 22:49 ` [PATCH v2 19/19] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230327224934.363314-8-dbarboza@ventanamicro.com \
--to=dbarboza@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.