From: Boris Brezillon <boris.brezillon@collabora.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, steven.price@arm.com,
robh+dt@kernel.org, alyssa.rosenzweig@collabora.com,
wenst@chromium.org, kernel@collabora.com
Subject: Re: [PATCH v1 RESEND 2/2] drm/panfrost: Add basic support for speed binning
Date: Fri, 31 Mar 2023 11:29:32 +0200 [thread overview]
Message-ID: <20230331112932.73b39d5a@collabora.com> (raw)
In-Reply-To: <fb19c82b-f2bf-7f22-ba5c-e1a1c98f987f@collabora.com>
On Fri, 31 Mar 2023 10:57:46 +0200
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
wrote:
> Il 31/03/23 10:49, Boris Brezillon ha scritto:
> > On Fri, 31 Mar 2023 10:11:07 +0200
> > AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > wrote:
> >
> >> Il 23/03/23 10:08, AngeloGioacchino Del Regno ha scritto:
> >>> Some SoCs implementing ARM Mali GPUs are subject to speed binning:
> >>> this means that some versions of the same SoC model may need to be
> >>> limited to a slower frequency compared to the other:
> >>> this is being addressed by reading nvmem (usually, an eFuse array)
> >>> containing a number that identifies the speed binning of the chip,
> >>> which is usually related to silicon quality.
> >>>
> >>> To address such situation, add basic support for reading the
> >>> speed-bin through nvmem, as to make it possible to specify the
> >>> supported hardware in the OPP table for GPUs.
> >>> This commit also keeps compatibility with any platform that does
> >>> not specify (and does not even support) speed-binning.
> >>>
> >>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Hello maintainers,
> >> I've seen that this got archived in the dri-devel patchwork; because of that and
> >> only that, I'm sending this ping to get this patch reviewed.
> >
> > Looks good to me. If you can get a DT maintainer to review the binding
> > (Rob?), I'd be happy to queue the series to drm-misc-next.
> >
>
> The binding was acked by Krzysztof already... so, just to be sure:
>
> Krzysztof, can the binding [1] get picked?
Oops, sorry, I didn't realize Krzysztof is a DT maintainer.
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, steven.price@arm.com,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
robh+dt@kernel.org, alyssa.rosenzweig@collabora.com,
wenst@chromium.org, kernel@collabora.com
Subject: Re: [PATCH v1 RESEND 2/2] drm/panfrost: Add basic support for speed binning
Date: Fri, 31 Mar 2023 11:29:32 +0200 [thread overview]
Message-ID: <20230331112932.73b39d5a@collabora.com> (raw)
In-Reply-To: <fb19c82b-f2bf-7f22-ba5c-e1a1c98f987f@collabora.com>
On Fri, 31 Mar 2023 10:57:46 +0200
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
wrote:
> Il 31/03/23 10:49, Boris Brezillon ha scritto:
> > On Fri, 31 Mar 2023 10:11:07 +0200
> > AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > wrote:
> >
> >> Il 23/03/23 10:08, AngeloGioacchino Del Regno ha scritto:
> >>> Some SoCs implementing ARM Mali GPUs are subject to speed binning:
> >>> this means that some versions of the same SoC model may need to be
> >>> limited to a slower frequency compared to the other:
> >>> this is being addressed by reading nvmem (usually, an eFuse array)
> >>> containing a number that identifies the speed binning of the chip,
> >>> which is usually related to silicon quality.
> >>>
> >>> To address such situation, add basic support for reading the
> >>> speed-bin through nvmem, as to make it possible to specify the
> >>> supported hardware in the OPP table for GPUs.
> >>> This commit also keeps compatibility with any platform that does
> >>> not specify (and does not even support) speed-binning.
> >>>
> >>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Hello maintainers,
> >> I've seen that this got archived in the dri-devel patchwork; because of that and
> >> only that, I'm sending this ping to get this patch reviewed.
> >
> > Looks good to me. If you can get a DT maintainer to review the binding
> > (Rob?), I'd be happy to queue the series to drm-misc-next.
> >
>
> The binding was acked by Krzysztof already... so, just to be sure:
>
> Krzysztof, can the binding [1] get picked?
Oops, sorry, I didn't realize Krzysztof is a DT maintainer.
next prev parent reply other threads:[~2023-03-31 9:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-23 9:08 [PATCH v1 RESEND 0/2] Panfrost: GPU Speed-binning support via OPP AngeloGioacchino Del Regno
2023-03-23 9:08 ` AngeloGioacchino Del Regno
2023-03-23 9:08 ` [PATCH v1 RESEND 1/2] dt-bindings: gpu: mali-bifrost: Document nvmem for speedbin support AngeloGioacchino Del Regno
2023-03-23 9:08 ` AngeloGioacchino Del Regno
2023-03-27 7:30 ` Krzysztof Kozlowski
2023-03-27 7:30 ` Krzysztof Kozlowski
2023-03-23 9:08 ` [PATCH v1 RESEND 2/2] drm/panfrost: Add basic support for speed binning AngeloGioacchino Del Regno
2023-03-23 9:08 ` AngeloGioacchino Del Regno
2023-03-31 8:11 ` AngeloGioacchino Del Regno
2023-03-31 8:11 ` AngeloGioacchino Del Regno
2023-03-31 8:49 ` Boris Brezillon
2023-03-31 8:49 ` Boris Brezillon
2023-03-31 8:57 ` AngeloGioacchino Del Regno
2023-03-31 8:57 ` AngeloGioacchino Del Regno
2023-03-31 9:29 ` Boris Brezillon [this message]
2023-03-31 9:29 ` Boris Brezillon
2023-03-31 9:46 ` Boris Brezillon
2023-03-31 9:46 ` Boris Brezillon
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