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From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>,
	William Qiu <william.qiu@starfivetech.com>
Subject: [PATCH v7 2/2] riscv: dts: starfive: jh7110: Add syscon nodes
Date: Thu, 6 Apr 2023 18:33:08 +0800	[thread overview]
Message-ID: <20230406103308.1280860-3-william.qiu@starfivetech.com> (raw)
In-Reply-To: <20230406103308.1280860-1-william.qiu@starfivetech.com>

Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..f271c3184d3a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,11 @@ i2c2: i2c@10050000 {
 			status = "disabled";
 		};

+		stg_syscon: syscon@10240000 {
+			compatible = "starfive,jh7110-stg-syscon", "syscon";
+			reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
@@ -457,6 +462,11 @@ syscrg: clock-controller@13020000 {
 			#reset-cells = <1>;
 		};

+		sys_syscon: syscon@13030000 {
+			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		sysgpio: pinctrl@13040000 {
 			compatible = "starfive,jh7110-sys-pinctrl";
 			reg = <0x0 0x13040000 0x0 0x10000>;
@@ -486,6 +496,11 @@ aoncrg: clock-controller@17000000 {
 			#reset-cells = <1>;
 		};

+		aon_syscon: syscon@17010000 {
+			compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
 		aongpio: pinctrl@17020000 {
 			compatible = "starfive,jh7110-aon-pinctrl";
 			reg = <0x0 0x17020000 0x0 0x10000>;
--
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>,
	William Qiu <william.qiu@starfivetech.com>
Subject: [PATCH v7 2/2] riscv: dts: starfive: jh7110: Add syscon nodes
Date: Thu, 6 Apr 2023 18:33:08 +0800	[thread overview]
Message-ID: <20230406103308.1280860-3-william.qiu@starfivetech.com> (raw)
In-Reply-To: <20230406103308.1280860-1-william.qiu@starfivetech.com>

Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..f271c3184d3a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,11 @@ i2c2: i2c@10050000 {
 			status = "disabled";
 		};

+		stg_syscon: syscon@10240000 {
+			compatible = "starfive,jh7110-stg-syscon", "syscon";
+			reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
@@ -457,6 +462,11 @@ syscrg: clock-controller@13020000 {
 			#reset-cells = <1>;
 		};

+		sys_syscon: syscon@13030000 {
+			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		sysgpio: pinctrl@13040000 {
 			compatible = "starfive,jh7110-sys-pinctrl";
 			reg = <0x0 0x13040000 0x0 0x10000>;
@@ -486,6 +496,11 @@ aoncrg: clock-controller@17000000 {
 			#reset-cells = <1>;
 		};

+		aon_syscon: syscon@17010000 {
+			compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
 		aongpio: pinctrl@17020000 {
 			compatible = "starfive,jh7110-aon-pinctrl";
 			reg = <0x0 0x17020000 0x0 0x10000>;
--
2.34.1


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  parent reply	other threads:[~2023-04-06 10:33 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-06 10:33 [PATCH v7 0/2] StarFive's SYSCON support William Qiu
2023-04-06 10:33 ` William Qiu
2023-04-06 10:33 ` [PATCH v7 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc William Qiu
2023-04-06 10:33   ` William Qiu
2023-04-06 18:30   ` Krzysztof Kozlowski
2023-04-06 18:30     ` Krzysztof Kozlowski
2023-04-07  9:30     ` William Qiu
2023-04-07  9:30       ` William Qiu
2023-04-07 10:11       ` Conor Dooley
2023-04-07 10:11         ` Conor Dooley
2023-04-07 11:17         ` William Qiu
2023-04-07 11:17           ` William Qiu
2023-04-06 10:33 ` William Qiu [this message]
2023-04-06 10:33   ` [PATCH v7 2/2] riscv: dts: starfive: jh7110: Add syscon nodes William Qiu
2023-04-29 18:58 ` [PATCH v7 0/2] StarFive's SYSCON support Palmer Dabbelt
2023-04-29 18:58   ` Palmer Dabbelt

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