From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Stefan Weil <sw@weilnetz.de>
Cc: <qemu-devel@nongnu.org>, <qemu-trivial@nongnu.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH for-8.0] docs/cxl: Fix sentence
Date: Tue, 11 Apr 2023 12:43:54 +0100 [thread overview]
Message-ID: <20230411124354.00006663@Huawei.com> (raw)
In-Reply-To: <20230409201828.1159568-1-sw@weilnetz.de>
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil <sw@weilnetz.de> wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Stefan Weil <sw@weilnetz.de>
Cc: <qemu-devel@nongnu.org>, <qemu-trivial@nongnu.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH for-8.0] docs/cxl: Fix sentence
Date: Tue, 11 Apr 2023 12:43:54 +0100 [thread overview]
Message-ID: <20230411124354.00006663@Huawei.com> (raw)
In-Reply-To: <20230409201828.1159568-1-sw@weilnetz.de>
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil <sw@weilnetz.de> wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.
next prev parent reply other threads:[~2023-04-11 11:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-09 20:18 [PATCH for-8.0] docs/cxl: Fix sentence Stefan Weil
2023-04-09 20:18 ` Stefan Weil via
2023-04-11 1:10 ` Richard Henderson
2023-04-11 7:08 ` Michael S. Tsirkin
2023-04-11 11:43 ` Jonathan Cameron [this message]
2023-04-11 11:43 ` Jonathan Cameron via
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