All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [RFC PATCH 11/14] KVM: selftests: riscv: Move sbi_ecall to processor.c
Date: Mon, 17 Apr 2023 12:33:59 +0200	[thread overview]
Message-ID: <20230417103402.798596-12-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230417103402.798596-1-ajones@ventanamicro.com>

sbi_ecall() isn't ucall specific. Move it to processor.c.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 .../selftests/kvm/lib/riscv/processor.c       | 26 +++++++++++++++++++
 tools/testing/selftests/kvm/lib/riscv/ucall.c | 26 -------------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index d146ca71e0c0..de67197ee848 100644
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -367,3 +367,29 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
 {
 }
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+			unsigned long arg1, unsigned long arg2,
+			unsigned long arg3, unsigned long arg4,
+			unsigned long arg5)
+{
+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+	struct sbiret ret;
+
+	asm volatile (
+		"ecall"
+		: "+r" (a0), "+r" (a1)
+		: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+		: "memory");
+	ret.error = a0;
+	ret.value = a1;
+
+	return ret;
+}
diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
index 9a3476a2dfca..ff6eef140293 100644
--- a/tools/testing/selftests/kvm/lib/riscv/ucall.c
+++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
@@ -14,32 +14,6 @@ void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
 {
 }
 
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
-			unsigned long arg1, unsigned long arg2,
-			unsigned long arg3, unsigned long arg4,
-			unsigned long arg5)
-{
-	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
-	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
-	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
-	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
-	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
-	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
-	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
-	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
-	struct sbiret ret;
-
-	asm volatile (
-		"ecall"
-		: "+r" (a0), "+r" (a1)
-		: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
-		: "memory");
-	ret.error = a0;
-	ret.value = a1;
-
-	return ret;
-}
-
 void ucall_arch_do_ucall(vm_vaddr_t uc)
 {
 	sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT,
-- 
2.39.2



WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
	virtualization@lists.linux-foundation.org
Cc: 'Paul Walmsley ' <paul.walmsley@sifive.com>,
	'Albert Ou ' <aou@eecs.berkeley.edu>,
	'Palmer Dabbelt ' <palmer@dabbelt.com>,
	'Paolo Bonzini ' <pbonzini@redhat.com>,
	'Juergen Gross ' <jgross@suse.com>,
	"'Srivatsa S . Bhat '" <srivatsa@csail.mit.edu>,
	'Anup Patel ' <anup@brainfault.org>,
	'Atish Patra ' <atishp@atishpatra.org>
Subject: [RFC PATCH 11/14] KVM: selftests: riscv: Move sbi_ecall to processor.c
Date: Mon, 17 Apr 2023 12:33:59 +0200	[thread overview]
Message-ID: <20230417103402.798596-12-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230417103402.798596-1-ajones@ventanamicro.com>

sbi_ecall() isn't ucall specific. Move it to processor.c.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 .../selftests/kvm/lib/riscv/processor.c       | 26 +++++++++++++++++++
 tools/testing/selftests/kvm/lib/riscv/ucall.c | 26 -------------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index d146ca71e0c0..de67197ee848 100644
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -367,3 +367,29 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
 {
 }
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+			unsigned long arg1, unsigned long arg2,
+			unsigned long arg3, unsigned long arg4,
+			unsigned long arg5)
+{
+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+	struct sbiret ret;
+
+	asm volatile (
+		"ecall"
+		: "+r" (a0), "+r" (a1)
+		: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+		: "memory");
+	ret.error = a0;
+	ret.value = a1;
+
+	return ret;
+}
diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
index 9a3476a2dfca..ff6eef140293 100644
--- a/tools/testing/selftests/kvm/lib/riscv/ucall.c
+++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
@@ -14,32 +14,6 @@ void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
 {
 }
 
-struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
-			unsigned long arg1, unsigned long arg2,
-			unsigned long arg3, unsigned long arg4,
-			unsigned long arg5)
-{
-	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
-	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
-	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
-	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
-	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
-	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
-	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
-	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
-	struct sbiret ret;
-
-	asm volatile (
-		"ecall"
-		: "+r" (a0), "+r" (a1)
-		: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
-		: "memory");
-	ret.error = a0;
-	ret.value = a1;
-
-	return ret;
-}
-
 void ucall_arch_do_ucall(vm_vaddr_t uc)
 {
 	sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT,
-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-04-17 10:33 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-17 10:33 [RFC PATCH 00/14] RISC-V: Add steal-time support Andrew Jones
2023-04-17 10:33 ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 01/14] RISC-V: paravirt: Add skeleton for pv-time support Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 02/14] RISC-V: Add SBI STA extension definitions Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-18 18:43   ` Conor Dooley
2023-04-18 18:44     ` Conor Dooley
2023-04-19  8:15     ` Andrew Jones
2023-04-19  8:15       ` Andrew Jones
2023-04-19 16:22       ` Conor Dooley
2023-04-19 16:22         ` Conor Dooley
2023-08-03  1:27       ` Guo Ren
2023-08-03  1:27         ` Guo Ren
2023-08-03  6:48         ` Andrew Jones
2023-08-03  6:48           ` Andrew Jones
2023-08-05  1:34           ` Guo Ren
2023-08-05  1:34             ` Guo Ren
2023-08-02 23:32   ` Guo Ren
2023-08-02 23:32     ` Guo Ren
2023-08-03  7:20     ` Andrew Jones
2023-08-03  7:20       ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 03/14] RISC-V: paravirt: Implement steal-time support Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-18 19:02   ` Conor Dooley
2023-04-18 19:02     ` Conor Dooley
2023-04-19  8:24     ` Andrew Jones
2023-04-19  8:24       ` Andrew Jones
2023-04-19 16:41       ` Conor Dooley
2023-04-19 16:42         ` Conor Dooley
2023-04-19  8:42   ` Andrew Jones
2023-04-19  8:42     ` Andrew Jones
2023-04-19 12:14     ` Andrew Jones
2023-04-19 12:14       ` Andrew Jones
2023-08-02 23:26     ` Guo Ren
2023-08-02 23:26       ` Guo Ren
2023-08-03  7:04       ` Andrew Jones
2023-08-03  7:04         ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 04/14] RISC-V: paravirt: Add kconfigs Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-18 19:08   ` Conor Dooley
2023-04-18 19:09     ` Conor Dooley
2023-04-17 10:33 ` [RFC PATCH 05/14] RISC-V: KVM: Add SBI STA extension skeleton Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 06/14] RISC-V: KVM: Add steal-update vcpu request Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 07/14] RISC-V: KVM: Add SBI STA info to vcpu_arch Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 08/14] RISC-V: KVM: Implement SBI STA extension Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 09/14] RISC-V: KVM: Add support for SBI extension registers Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` [RFC PATCH 10/14] RISC-V: KVM: Add support for SBI STA registers Andrew Jones
2023-04-17 10:33   ` Andrew Jones
2023-04-17 10:33 ` Andrew Jones [this message]
2023-04-17 10:33   ` [RFC PATCH 11/14] KVM: selftests: riscv: Move sbi_ecall to processor.c Andrew Jones
2023-04-17 10:34 ` [RFC PATCH 12/14] KVM: selftests: riscv: Add guest_sbi_probe_extension Andrew Jones
2023-04-17 10:34   ` Andrew Jones
2023-04-17 10:34 ` [RFC PATCH 13/14] KVM: selftests: riscv: Add RISCV_SBI_EXT_REG Andrew Jones
2023-04-17 10:34   ` Andrew Jones
2023-04-17 10:34 ` [RFC PATCH 14/14] KVM: selftests: riscv: Add steal_time test support Andrew Jones
2023-04-17 10:34   ` Andrew Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230417103402.798596-12-ajones@ventanamicro.com \
    --to=ajones@ventanamicro.com \
    --cc=kvm-riscv@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.