From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Nick Desaulniers <ndesaulniers@google.com>,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
llvm@lists.linux.dev, Nathan Chancellor <nathan@kernel.org>
Subject: Re: [PATCH 1/8] MIPS: Replace assembly isa level directives with macros
Date: Fri, 21 Apr 2023 09:41:35 +0200 [thread overview]
Message-ID: <20230421074134.GA6209@alpha.franken.de> (raw)
In-Reply-To: <FEE1072C-2228-4B2E-92C0-760F0B471D04@flygoat.com>
On Thu, Apr 20, 2023 at 08:29:03PM +0100, Jiaxun Yang wrote:
> Yes, GAS and LLVM sometimes have different opinions on what a instruction
> feature should belong to. Personally I think there is no right or wrong in most case.
>
> So generally when we try to use some inline assembly features that toolchain
> may consider belongs to higher ISA level we will use `.set mips64r2` directives.
>
> Having this patch just unified the defined arch across the tree, so it happens to fix
> some cases where `.set` was given a improper option.
I'd prefer, if we don't magically fix something by doing this massive
replacement. So first bug fixing then cleanup.
And what I don't like is the name of the #defines (I know it's not your
choice, ), they don't tell me anything and it's still not clear which
one should be used in which case.
I see one use case, which is enabling 64bit instruction inside a 32bit
kernel.
What are the others ?
Do we really need all of them ? For example the change in
arch/mips/mm/cex-oct.S, this is for a octeon kernel, which only supports
and works with 64bit kernels...
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2023-04-21 7:44 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-09 10:43 [PATCH 0/7] MIPS: LLVM build fixes Jiaxun Yang
2023-04-09 10:43 ` [PATCH 1/8] MIPS: Replace assembly isa level directives with macros Jiaxun Yang
2023-04-20 16:43 ` Nick Desaulniers
2023-04-20 19:29 ` Jiaxun Yang
2023-04-21 7:41 ` Thomas Bogendoerfer [this message]
2023-04-21 8:18 ` Jiaxun Yang
2023-04-21 13:01 ` Maciej W. Rozycki
2023-04-09 10:43 ` [PATCH 2/8] MIPS: Set ISA level for MSA control reg helpers Jiaxun Yang
2023-04-09 10:43 ` [PATCH 3/8] MIPS: loongson2ef: Add missing break in cs5536_isa Jiaxun Yang
2023-04-12 13:31 ` Thomas Bogendoerfer
2023-04-09 10:43 ` [PATCH 4/8] MIPS: asmmacro: Restore fp macro after undef Jiaxun Yang
2023-04-09 10:43 ` [PATCH 5/8] MIPS: mipsregs: Parse fp and sp register by name in parse_r Jiaxun Yang
2023-04-21 10:48 ` Thomas Bogendoerfer
2023-04-21 11:38 ` Jiaxun Yang
2023-04-21 12:21 ` Thomas Bogendoerfer
2023-04-21 12:42 ` Jiaxun Yang
2023-04-09 10:43 ` [PATCH 6/8] MIPS: c-r4k: Use cache_op function for rm7k_erratum31 Jiaxun Yang
2023-04-09 10:43 ` [PATCH 7/8] MIPS: octeon_switch: Remove duplicated labels Jiaxun Yang
2023-04-12 13:31 ` Thomas Bogendoerfer
2023-04-09 10:43 ` [PATCH 8/8] MIPS: Implement microMIPS MT ASE helpers Jiaxun Yang
2023-04-21 8:31 ` [PATCH 0/7] MIPS: LLVM build fixes Jiaxun Yang
-- strict thread matches above, loose matches on Subject: below --
2023-04-11 11:12 Jiaxun Yang
2023-04-11 11:12 ` [PATCH 1/8] MIPS: Replace assembly isa level directives with macros Jiaxun Yang
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