From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Lukas Wunner <lukas@wunner.de>, <linux-cxl@vger.kernel.org>,
<ira.weiny@intel.com>
Subject: Re: [PATCH] cxl/port: Fix port to pci device assumptions in read_cdat_data()
Date: Sun, 23 Apr 2023 15:58:03 +0100 [thread overview]
Message-ID: <20230423155803.00001807@huawei.com> (raw)
In-Reply-To: <644449f43a352_1b662947a@dwillia2-xfh.jf.intel.com.notmuch>
On Sat, 22 Apr 2023 13:56:20 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Lukas Wunner wrote:
> > On Fri, Apr 21, 2023 at 07:51:47PM -0700, Dan Williams wrote:
> > > Not all CXL ports are associated with PCI devices. Host-bridge and
> > > cxl_test ports are hosted by platform devices. Teach read_cdat_data() to
> > > be careful about non-pci hosted cxl_memdev instances. Otherwise,
> > > cxl_test crashes with this signature:
> > >
> > > RIP: 0010:xas_start+0x6d/0x290
> > > [..]
> > > Call Trace:
> > > <TASK>
> > > xas_load+0xa/0x50
> > > xas_find+0x25b/0x2f0
> > > xa_find+0x118/0x1d0
> > > pci_find_doe_mailbox+0x51/0xc0
> > > read_cdat_data+0x45/0x190 [cxl_core]
> > > cxl_port_probe+0x10a/0x1e0 [cxl_port]
> > > cxl_bus_probe+0x17/0x50 [cxl_core]
> > >
> > > Some other cleanups are included like removing the single-use @uport
> > > variable, and removing the indirection through 'struct cxl_dev_state' to
> > > lookup the device that registered the memdev and may be a pci device.
> > >
> > > Fixes: af0a6c3587dc ("cxl/pci: Use CDAT DOE mailbox created by PCI core")
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> >
> > Reviewed-by: Lukas Wunner <lukas@wunner.de>
> >
> > Take my Reviewed-by with a grain of salt as I'm absolutely not an
> > expert on the cxl struct hierarchy, nevertheless this looks sane to me.
>
> Yeah, I think we need a data structure relationship diagram to explain
> endpoint devices, memory devices, endpoint ports, and switch ports all
> interconnect.
Agreed. I keep forgetting how this all works as well and end up scattering
prints everywhere to find out.
A diagram to refer to would be very useful.
Jonathan
>
> > I note however that before af0a6c3587dc, xa_for_each() was run on an
> > xarray which was not initialized with xa_init() on non-pci cxl ports.
> > (xa_init() was run from cxl_pci_probe() -> devm_cxl_pci_create_doe()
> > but xa_for_each() was run from read_cdat_data() -> find_cdat_doe()
> > for non-pci cxl ports as well.)
> >
> > Hence can't this crash prior to af0a6c3587dc as well? If it can,
> > the Fixes tag would rather have to point to c97006046c79 ("cxl/port:
> > Read CDAT table"), though this patch wouldn't apply cleanly to
> > pre-6.4 kernels. c97006046c79 went into v6.0 and there's one stable
> > kernel between it and v6.4 (for which af0a6c3587dc is queued).
> > So if the missing xa_init() can indeed cause crashes, you may want to
> > base your fix on v6.3 and fold it in at the front of cxl/next,
> > then rebase af0a6c3587dc on top of it. Let me know if you need help
> > or want me to look into it.
>
> As I replied on the other note, I think older kernels are ok.
>
> > Thanks for fixing this and sorry for not spotting it myself!
>
> No worries, I had missed that the unit test were not run yet.
next prev parent reply other threads:[~2023-04-23 14:58 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-11 14:40 [PATCH v4 00/17] Collection of DOE material Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 01/17] cxl/pci: Fix CDAT retrieval on big endian Lukas Wunner
2023-03-15 16:39 ` Jonathan Cameron
2023-03-11 14:40 ` [PATCH v4 02/17] cxl/pci: Handle truncated CDAT header Lukas Wunner
2023-03-13 2:42 ` Sathyanarayanan Kuppuswamy
2023-03-11 14:40 ` [PATCH v4 03/17] cxl/pci: Handle truncated CDAT entries Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 04/17] cxl/pci: Handle excessive CDAT length Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 05/17] PCI/DOE: Silence WARN splat with CONFIG_DEBUG_OBJECTS=y Lukas Wunner
2023-03-21 3:42 ` Alexey Kardashevskiy
2023-03-21 9:05 ` Jonathan Cameron
2023-04-04 9:01 ` Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 06/17] PCI/DOE: Fix memory leak " Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 07/17] PCI/DOE: Provide synchronous API and use it internally Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 08/17] cxl/pci: Use synchronous API for DOE Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 09/17] PCI/DOE: Make asynchronous API private Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 10/17] PCI/DOE: Deduplicate mailbox flushing Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 11/17] PCI/DOE: Allow mailbox creation without devres management Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 12/17] PCI/DOE: Create mailboxes on device enumeration Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 13/17] cxl/pci: Use CDAT DOE mailbox created by PCI core Lukas Wunner
2023-04-22 2:51 ` [PATCH] cxl/port: Fix port to pci device assumptions in read_cdat_data() Dan Williams
2023-04-22 8:35 ` Lukas Wunner
2023-04-22 14:05 ` Lukas Wunner
2023-04-22 20:54 ` Dan Williams
2023-04-22 22:30 ` Lukas Wunner
2023-04-22 23:22 ` Dan Williams
2023-04-23 8:19 ` Lukas Wunner
2023-04-22 20:56 ` Dan Williams
2023-04-23 14:58 ` Jonathan Cameron [this message]
2023-04-23 15:07 ` Jonathan Cameron
2023-04-23 18:32 ` Dan Williams
2023-03-11 14:40 ` [PATCH v4 14/17] PCI/DOE: Make mailbox creation API private Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 15/17] PCI/DOE: Relax restrictions on request and response size Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 16/17] cxl/pci: Simplify CDAT retrieval error path Lukas Wunner
2023-03-15 16:48 ` Jonathan Cameron
2023-03-11 14:40 ` [PATCH v4 17/17] cxl/pci: Rightsize CDAT response allocation Lukas Wunner
2023-03-13 19:55 ` [PATCH v4 00/17] Collection of DOE material Bjorn Helgaas
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