From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <ira.weiny@intel.com>, <lukas@wunner.de>
Subject: Re: [PATCH] cxl/port: Fix port to pci device assumptions in read_cdat_data()
Date: Sun, 23 Apr 2023 16:07:00 +0100 [thread overview]
Message-ID: <20230423160700.00007340@huawei.com> (raw)
In-Reply-To: <168213190748.708404.16215095414060364800.stgit@dwillia2-xfh.jf.intel.com>
On Fri, 21 Apr 2023 19:51:47 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Not all CXL ports are associated with PCI devices. Host-bridge and
> cxl_test ports are hosted by platform devices. Teach read_cdat_data() to
> be careful about non-pci hosted cxl_memdev instances. Otherwise,
> cxl_test crashes with this signature:
This is crossing two paths. One memdevs that aren't hosted by
PCI devices, two the other port cases. Right now this code assumes
a memdev, so calling out the other case is problematic.
I'd just drop the mention of host bridges or mention that we only
call this for memdev ports today.
>
> RIP: 0010:xas_start+0x6d/0x290
> [..]
> Call Trace:
> <TASK>
> xas_load+0xa/0x50
> xas_find+0x25b/0x2f0
> xa_find+0x118/0x1d0
> pci_find_doe_mailbox+0x51/0xc0
> read_cdat_data+0x45/0x190 [cxl_core]
> cxl_port_probe+0x10a/0x1e0 [cxl_port]
> cxl_bus_probe+0x17/0x50 [cxl_core]
>
> Some other cleanups are included like removing the single-use @uport
> variable, and removing the indirection through 'struct cxl_dev_state' to
> lookup the device that registered the memdev and may be a pci device.
>
> Fixes: af0a6c3587dc ("cxl/pci: Use CDAT DOE mailbox created by PCI core")
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Makes sense. If it's not a PCI device no config space so no DOE instance
(+ the wrong device types etc).
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/pci.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 25b7e8125d5d..bdbd907884ce 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -536,17 +536,18 @@ static int cxl_cdat_read_table(struct device *dev,
> */
> void read_cdat_data(struct cxl_port *port)
> {
> - struct pci_doe_mb *cdat_doe;
> + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
Given you talk about host bridges above, this would not be safe
I don't think we call this on host bridges though so perhaps the
patch description needs to not mention them to avoid confusion.
> + struct device *host = cxlmd->dev.parent;
> struct device *dev = &port->dev;
> - struct device *uport = port->uport;
> - struct cxl_memdev *cxlmd = to_cxl_memdev(uport);
> - struct cxl_dev_state *cxlds = cxlmd->cxlds;
> - struct pci_dev *pdev = to_pci_dev(cxlds->dev);
> + struct pci_doe_mb *cdat_doe;
> size_t cdat_length;
> void *cdat_table;
> int rc;
>
> - cdat_doe = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,
> + if (!dev_is_pci(host))
> + return;
> + cdat_doe = pci_find_doe_mailbox(to_pci_dev(host),
> + PCI_DVSEC_VENDOR_ID_CXL,
> CXL_DOE_PROTOCOL_TABLE_ACCESS);
> if (!cdat_doe) {
> dev_dbg(dev, "No CDAT mailbox\n");
>
next prev parent reply other threads:[~2023-04-23 15:07 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-11 14:40 [PATCH v4 00/17] Collection of DOE material Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 01/17] cxl/pci: Fix CDAT retrieval on big endian Lukas Wunner
2023-03-15 16:39 ` Jonathan Cameron
2023-03-11 14:40 ` [PATCH v4 02/17] cxl/pci: Handle truncated CDAT header Lukas Wunner
2023-03-13 2:42 ` Sathyanarayanan Kuppuswamy
2023-03-11 14:40 ` [PATCH v4 03/17] cxl/pci: Handle truncated CDAT entries Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 04/17] cxl/pci: Handle excessive CDAT length Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 05/17] PCI/DOE: Silence WARN splat with CONFIG_DEBUG_OBJECTS=y Lukas Wunner
2023-03-21 3:42 ` Alexey Kardashevskiy
2023-03-21 9:05 ` Jonathan Cameron
2023-04-04 9:01 ` Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 06/17] PCI/DOE: Fix memory leak " Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 07/17] PCI/DOE: Provide synchronous API and use it internally Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 08/17] cxl/pci: Use synchronous API for DOE Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 09/17] PCI/DOE: Make asynchronous API private Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 10/17] PCI/DOE: Deduplicate mailbox flushing Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 11/17] PCI/DOE: Allow mailbox creation without devres management Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 12/17] PCI/DOE: Create mailboxes on device enumeration Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 13/17] cxl/pci: Use CDAT DOE mailbox created by PCI core Lukas Wunner
2023-04-22 2:51 ` [PATCH] cxl/port: Fix port to pci device assumptions in read_cdat_data() Dan Williams
2023-04-22 8:35 ` Lukas Wunner
2023-04-22 14:05 ` Lukas Wunner
2023-04-22 20:54 ` Dan Williams
2023-04-22 22:30 ` Lukas Wunner
2023-04-22 23:22 ` Dan Williams
2023-04-23 8:19 ` Lukas Wunner
2023-04-22 20:56 ` Dan Williams
2023-04-23 14:58 ` Jonathan Cameron
2023-04-23 15:07 ` Jonathan Cameron [this message]
2023-04-23 18:32 ` Dan Williams
2023-03-11 14:40 ` [PATCH v4 14/17] PCI/DOE: Make mailbox creation API private Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 15/17] PCI/DOE: Relax restrictions on request and response size Lukas Wunner
2023-03-11 14:40 ` [PATCH v4 16/17] cxl/pci: Simplify CDAT retrieval error path Lukas Wunner
2023-03-15 16:48 ` Jonathan Cameron
2023-03-11 14:40 ` [PATCH v4 17/17] cxl/pci: Rightsize CDAT response allocation Lukas Wunner
2023-03-13 19:55 ` [PATCH v4 00/17] Collection of DOE material Bjorn Helgaas
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