From: Qiming Yang <qiming.yang@intel.com>
To: dev@dpdk.org
Cc: qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,
Yahui Cao <yahui.cao@intel.com>
Subject: [PATCH 13/30] net/ice/base: add function to get rxq context
Date: Thu, 27 Apr 2023 06:19:44 +0000 [thread overview]
Message-ID: <20230427062001.478032-14-qiming.yang@intel.com> (raw)
In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com>
This patch exports rxq context which is consumed by linux linve
migration driver to save device state.
Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_common.c | 75 +++++++++++++++++++++++++++----
drivers/net/ice/base/ice_common.h | 7 ++-
2 files changed, 71 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 58da198d62..ed822afc30 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1397,6 +1397,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
return ICE_SUCCESS;
}
+/**
+ * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW
+ * @hw: pointer to the hardware structure
+ * @ice_rxq_ctx: pointer to the rxq context
+ * @rxq_index: the index of the Rx queue
+ *
+ * Copies rxq context from HW register space to dense structure
+ */
+static enum ice_status
+ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
+{
+ u8 i;
+
+ if (!ice_rxq_ctx)
+ return ICE_ERR_BAD_PTR;
+
+ if (rxq_index > QRX_CTRL_MAX_INDEX)
+ return ICE_ERR_PARAM;
+
+ /* Copy each dword separately from HW */
+ for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
+ u32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32)));
+
+ *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index));
+
+ ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx);
+ }
+
+ return ICE_SUCCESS;
+}
+
/* LAN Rx Queue Context */
static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
/* Field Width LSB */
@@ -1448,6 +1479,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
}
+/**
+ * ice_read_rxq_ctx - Read rxq context from HW
+ * @hw: pointer to the hardware structure
+ * @rlan_ctx: pointer to the rxq context
+ * @rxq_index: the index of the Rx queue
+ *
+ * Read rxq context from HW register space and then converts it from dense
+ * structure to sparse
+ */
+enum ice_status
+ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
+ u32 rxq_index)
+{
+ u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
+ enum ice_status status;
+
+ if (!rlan_ctx)
+ return ICE_ERR_BAD_PTR;
+
+ status = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index);
+ if (status)
+ return status;
+
+ return ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info);
+}
+
/**
* ice_clear_rxq_ctx
* @hw: pointer to the hardware structure
@@ -4883,7 +4940,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
* @ce_info: a description of the struct to be filled
*/
static void
-ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
{
u8 dest_byte, mask;
u8 *src, *target;
@@ -4901,7 +4958,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
- dest_byte &= ~(mask);
+ dest_byte &= mask;
dest_byte >>= shift_width;
@@ -4919,7 +4976,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
* @ce_info: a description of the struct to be filled
*/
static void
-ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
{
u16 dest_word, mask;
u8 *src, *target;
@@ -4941,7 +4998,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
/* the data in the memory is stored as little endian so mask it
* correctly
*/
- src_word &= ~(CPU_TO_LE16(mask));
+ src_word &= CPU_TO_LE16(mask);
/* get the data back into host order before shifting */
dest_word = LE16_TO_CPU(src_word);
@@ -4962,7 +5019,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
* @ce_info: a description of the struct to be filled
*/
static void
-ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
{
u32 dest_dword, mask;
__le32 src_dword;
@@ -4992,7 +5049,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
/* the data in the memory is stored as little endian so mask it
* correctly
*/
- src_dword &= ~(CPU_TO_LE32(mask));
+ src_dword &= CPU_TO_LE32(mask);
/* get the data back into host order before shifting */
dest_dword = LE32_TO_CPU(src_dword);
@@ -5013,7 +5070,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
* @ce_info: a description of the struct to be filled
*/
static void
-ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
{
u64 dest_qword, mask;
__le64 src_qword;
@@ -5043,7 +5100,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
/* the data in the memory is stored as little endian so mask it
* correctly
*/
- src_qword &= ~(CPU_TO_LE64(mask));
+ src_qword &= CPU_TO_LE64(mask);
/* get the data back into host order before shifting */
dest_qword = LE64_TO_CPU(src_qword);
@@ -5064,7 +5121,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
* @ce_info: a description of the structure to be read from
*/
enum ice_status
-ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
{
int f;
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index d8fb7a6163..3e03f2e903 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -92,6 +92,9 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
enum ice_status
ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
u32 rxq_index);
+enum ice_status
+ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
+ u32 rxq_index);
enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
enum ice_status
ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
@@ -135,6 +138,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[];
enum ice_status
ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
const struct ice_ctx_ele *ce_info);
+enum ice_status
+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
enum ice_status
ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
@@ -229,8 +234,6 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
u32 start_address, u8 *buf, u8 buf_size,
struct ice_sq_cd *cd);
-enum ice_status
-ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
enum ice_status
ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
u16 *q_handle, u16 *q_ids, u32 *q_teids,
--
2.25.1
next prev parent reply other threads:[~2023-04-27 6:39 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-27 6:19 [PATCH 00/30] net/ice/base: share code update Qiming Yang
2023-04-27 6:19 ` [PATCH 01/30] net/ice/base: updated copyright Qiming Yang
2023-04-27 6:19 ` [PATCH 02/30] net/ice/base: add flex array safe allocations Qiming Yang
2023-04-27 6:19 ` [PATCH 03/30] net/ice/base: remove unnecessary control queue array Qiming Yang
2024-03-05 18:05 ` [**EXTERNAL**] " Gudimetla, Leela Sankar
2023-04-27 6:19 ` [PATCH 04/30] net/ice/base: update flow seg fields to declared bitmaps Qiming Yang
2023-04-27 6:19 ` [PATCH 05/30] net/ice/base: clean up RSS LUT and fix media type Qiming Yang
2023-04-27 6:19 ` [PATCH 06/30] net/ice/base: add ability to set markid via switch filter Qiming Yang
2023-04-27 6:19 ` [PATCH 07/30] net/ice/base: add reading cap and ropo cap Qiming Yang
2023-04-27 6:19 ` [PATCH 08/30] net/ice/base: add function to read HW sensors Qiming Yang
2023-04-27 6:19 ` [PATCH 09/30] net/ice/base: add pre-allocate memory argument Qiming Yang
2023-04-27 6:19 ` [PATCH 10/30] net/ice/base: use coccinelle to instead macro Qiming Yang
2023-04-27 6:19 ` [PATCH 11/30] net/ice/base: add new fls function Qiming Yang
2023-04-27 6:19 ` [PATCH 12/30] net/ice/base: add E830 device ids Qiming Yang
2023-04-27 6:19 ` Qiming Yang [this message]
2023-04-27 6:19 ` [PATCH 14/30] net/ice/base: removed no need 56G releated code Qiming Yang
2023-04-27 6:19 ` [PATCH 15/30] net/ice/base: allow skip main timer Qiming Yang
2023-04-27 6:19 ` [PATCH 16/30] net/ice/base: add E830 PTP init Qiming Yang
2023-04-27 6:19 ` [PATCH 17/30] net/ice/base: add C825X device support Qiming Yang
2023-04-27 6:19 ` [PATCH 18/30] net/ice/base: add VLAN TPID in switchdev Qiming Yang
2023-04-27 6:19 ` [PATCH 19/30] net/ice/base: reduce time to read Option ROM CIVD Qiming Yang
2023-04-27 6:19 ` [PATCH 20/30] net/ice/base: add L2TPv3 support for adv rules Qiming Yang
2023-04-27 6:19 ` [PATCH 21/30] net/ice/base: add PHY OFFSET READY register clear Qiming Yang
2023-04-27 6:19 ` [PATCH 22/30] net/ice/base: return CGU PLL config function params Qiming Yang
2023-04-27 6:19 ` [PATCH 23/30] net/ice/base: change method to get pca9575 handle Qiming Yang
2023-04-27 6:19 ` [PATCH 24/30] net/ice/base: cleanup timestamp registers correct Qiming Yang
2023-04-27 6:19 ` [PATCH 25/30] net/ice/base: add PPPoE hardware offload Qiming Yang
2023-04-27 6:19 ` [PATCH 26/30] net/ice/base: remove bypass mode Qiming Yang
2023-04-27 6:19 ` [PATCH 27/30] net/ice/base: support inner etype in switchdev Qiming Yang
2023-04-27 6:19 ` [PATCH 28/30] net/ice/base: use const array to store link modes Qiming Yang
2023-04-27 6:20 ` [PATCH 29/30] net/ice/base: introduce a new ID for E810 NIC Qiming Yang
2023-04-27 6:20 ` [PATCH 30/30] net/ice/base: fix Generic Checksum acronym Qiming Yang
2023-04-27 21:18 ` Greenwalt, Paul
2023-05-18 15:16 ` [PATCH v2 00/20] net/ice/base: code update Qiming Yang
2023-05-18 15:16 ` [PATCH v2 01/20] net/ice/base: updated copyright Qiming Yang
2023-05-18 15:16 ` [PATCH v2 02/20] net/ice/base: add NAC Topology device capability parser Qiming Yang
2023-05-18 15:16 ` [PATCH v2 03/20] net/ice/base: add new device for E810 Qiming Yang
2023-05-18 15:16 ` [PATCH v2 04/20] net/ice/base: fix incorrect defines for DCBx Qiming Yang
2023-05-18 15:16 ` [PATCH v2 05/20] net/ice/base: introduce a non-atomic function Qiming Yang
2023-05-18 15:16 ` [PATCH v2 06/20] net/ice/base: add missing AQ flag to AQ command Qiming Yang
2023-05-18 15:16 ` [PATCH v2 07/20] net/ice/base: add support for inner etype in switchdev Qiming Yang
2023-05-18 15:16 ` [PATCH v2 08/20] net/ice/base: add support for PPPoE hardware offload Qiming Yang
2023-05-18 15:16 ` [PATCH v2 09/20] net/ice/base: remove direction metadata for switchdev Qiming Yang
2023-05-18 15:16 ` [PATCH v2 10/20] net/ice/base: reduce time to read Option data Qiming Yang
2023-05-18 17:08 ` Keller, Jacob E
2023-05-18 15:16 ` [PATCH v2 11/20] net/ice/base: add support for VLAN TPID filters Qiming Yang
2023-05-18 15:16 ` [PATCH v2 12/20] net/ice/base: add C825-X device ID Qiming Yang
2023-05-18 15:16 ` [PATCH v2 13/20] net/ice/base: add function to get rxq context Qiming Yang
2023-05-18 15:16 ` [PATCH v2 14/20] net/ice/base: modify tunnel match mask Qiming Yang
2023-05-18 15:16 ` [PATCH v2 15/20] net/ice/base: check VSIG before disassociating VSI Qiming Yang
2023-05-18 15:16 ` [PATCH v2 16/20] net/ice/base: delete get field vector function Qiming Yang
2023-05-18 15:16 ` [PATCH v2 17/20] net/ice/base: update 3k-sign DDP support for E825C Qiming Yang
2023-05-18 15:16 ` [PATCH v2 18/20] net/ice/base: fix static analyzer bug Qiming Yang
2023-05-18 15:16 ` [PATCH v2 19/20] net/ice/base: offer memory config for schedual node Qiming Yang
2023-05-18 15:16 ` [PATCH v2 20/20] net/ice/base: add new AQ ro read HW sensors Qiming Yang
2023-05-23 2:12 ` [PATCH v2 00/20] net/ice/base: code update Zhang, Qi Z
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