From: kernel test robot <lkp@intel.com>
To: Vadim Fedorenko <vadfed@meta.com>
Cc: oe-kbuild-all@lists.linux.dev
Subject: Re: [RFC PATCH v7 4/8] ice: add admin commands to access cgu configuration
Date: Sat, 29 Apr 2023 01:53:00 +0800 [thread overview]
Message-ID: <202304290110.EXkC5dHd-lkp@intel.com> (raw)
In-Reply-To: <20230428002009.2948020-5-vadfed@meta.com>
Hi Vadim,
[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:
[auto build test WARNING on v6.3]
[cannot apply to tnguy-next-queue/dev-queue linus/master next-20230427]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Vadim-Fedorenko/dpll-spec-Add-Netlink-spec-in-YAML/20230428-082340
base: 457391b0380335d5e9a5babdec90ac53928b23b4
patch link: https://lore.kernel.org/r/20230428002009.2948020-5-vadfed%40meta.com
patch subject: [RFC PATCH v7 4/8] ice: add admin commands to access cgu configuration
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20230429/202304290110.EXkC5dHd-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/13ef3b4ad86b654d71f1e13448b0968c83403d02
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Vadim-Fedorenko/dpll-spec-Add-Netlink-spec-in-YAML/20230428-082340
git checkout 13ef3b4ad86b654d71f1e13448b0968c83403d02
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 olddefconfig
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202304290110.EXkC5dHd-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/bits.h:6,
from include/linux/bitops.h:6,
from include/linux/kernel.h:22,
from include/linux/skbuff.h:13,
from include/linux/ip.h:16,
from drivers/infiniband/hw/irdma/main.h:6,
from drivers/infiniband/hw/irdma/main.c:3:
drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:196:46: error: 'DPLL_PIN_FREQ_SUPP_1_HZ' undeclared here (not in a function); did you mean 'DPLL_PIN_FREQUENCY_1_HZ'?
196 | #define ICE_SIG_TYPE_MASK_1PPS_10MHZ (BIT(DPLL_PIN_FREQ_SUPP_1_HZ) | \
| ^~~~~~~~~~~~~~~~~~~~~~~
include/vdso/bits.h:7:44: note: in definition of macro 'BIT'
7 | #define BIT(nr) (UL(1) << (nr))
| ^~
drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:207:17: note: in expansion of macro 'ICE_SIG_TYPE_MASK_1PPS_10MHZ'
207 | ICE_SIG_TYPE_MASK_1PPS_10MHZ },
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:197:46: error: 'DPLL_PIN_FREQ_SUPP_10_MHZ' undeclared here (not in a function); did you mean 'DPLL_PIN_FREQUENCY_10_MHZ'?
197 | BIT(DPLL_PIN_FREQ_SUPP_10_MHZ))
| ^~~~~~~~~~~~~~~~~~~~~~~~~
include/vdso/bits.h:7:44: note: in definition of macro 'BIT'
7 | #define BIT(nr) (UL(1) << (nr))
| ^~
drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:207:17: note: in expansion of macro 'ICE_SIG_TYPE_MASK_1PPS_10MHZ'
207 | ICE_SIG_TYPE_MASK_1PPS_10MHZ },
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:211:21: error: 'DPLL_PIN_FREQ_SUPP_UNSPEC' undeclared here (not in a function); did you mean 'DPLL_PIN_DIRECTION_UNSPEC'?
211 | BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
| ^~~~~~~~~~~~~~~~~~~~~~~~~
include/vdso/bits.h:7:44: note: in definition of macro 'BIT'
7 | #define BIT(nr) (UL(1) << (nr))
| ^~
In file included from drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp.h:10,
from drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice.h:69,
from drivers/infiniband/hw/irdma/main.c:4:
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:325:38: warning: 'ice_e823_zl_cgu_outputs' defined but not used [-Wunused-const-variable=]
325 | static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:306:38: warning: 'ice_e823_zl_cgu_inputs' defined but not used [-Wunused-const-variable=]
306 | static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:295:38: warning: 'ice_e823_si_cgu_outputs' defined but not used [-Wunused-const-variable=]
295 | static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:279:38: warning: 'ice_e823_si_cgu_inputs' defined but not used [-Wunused-const-variable=]
279 | static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:262:38: warning: 'ice_e810t_qsfp_cgu_outputs' defined but not used [-Wunused-const-variable=]
262 | static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:247:38: warning: 'ice_e810t_sfp_cgu_outputs' defined but not used [-Wunused-const-variable=]
247 | static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:224:38: warning: 'ice_e810t_qsfp_cgu_inputs' defined but not used [-Wunused-const-variable=]
224 | static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h:205:38: warning: 'ice_e810t_sfp_cgu_inputs' defined but not used [-Wunused-const-variable=]
205 | static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~
vim +/ice_e823_zl_cgu_outputs +325 drivers/infiniband/hw/irdma/../../../net/ethernet/intel/ice/ice_ptp_hw.h
204
> 205 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
206 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
207 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
208 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
209 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
210 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX,
211 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
212 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX,
213 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
214 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
215 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
216 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
217 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
218 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
219 BIT(DPLL_PIN_FREQ_SUPP_1_HZ) },
220 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR,
221 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
222 };
223
> 224 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
225 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
226 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
227 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
228 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
229 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX,
230 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
231 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX,
232 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
233 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX,
234 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
235 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX,
236 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
237 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
238 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
239 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
240 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
241 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
242 BIT(DPLL_PIN_FREQ_SUPP_1_HZ) },
243 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR,
244 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
245 };
246
> 247 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
248 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
249 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
250 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
251 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
252 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
253 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
254 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
255 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
256 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
257 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
258 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
259 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
260 };
261
> 262 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
263 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
264 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
265 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
266 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
267 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
268 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
269 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
270 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
271 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
272 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
273 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
274 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
275 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
276 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
277 };
278
> 279 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
280 { "NONE", SI_REF0P, DPLL_PIN_TYPE_UNSPEC, 0 },
281 { "NONE", SI_REF0N, DPLL_PIN_TYPE_UNSPEC, 0 },
282 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX,
283 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
284 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX,
285 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
286 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
287 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
288 { "NONE", SI_REF2N, DPLL_PIN_TYPE_UNSPEC, 0 },
289 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
290 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
291 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
292 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
293 };
294
> 295 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
296 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
297 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
298 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
299 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
300 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
301 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
302 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
303 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
304 };
305
> 306 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
307 { "NONE", ZL_REF0P, DPLL_PIN_TYPE_UNSPEC, 0 },
308 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
309 BIT(DPLL_PIN_FREQ_SUPP_1_HZ) },
310 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX,
311 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
312 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX,
313 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
314 { "NONE", ZL_REF2P, DPLL_PIN_TYPE_UNSPEC, 0 },
315 { "NONE", ZL_REF2N, DPLL_PIN_TYPE_UNSPEC, 0 },
316 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
317 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
318 { "NONE", ZL_REF3N, DPLL_PIN_TYPE_UNSPEC, 0 },
319 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
320 BIT(DPLL_PIN_FREQ_SUPP_1_HZ) },
321 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR,
322 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
323 };
324
> 325 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
326 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
327 BIT(DPLL_PIN_FREQ_SUPP_1_HZ) },
328 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
329 BIT(DPLL_PIN_FREQ_SUPP_10_MHZ) },
330 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
331 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
332 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,
333 BIT(DPLL_PIN_FREQ_SUPP_UNSPEC) },
334 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
335 ICE_SIG_TYPE_MASK_1PPS_10MHZ },
336 { "NONE", ZL_OUT5, DPLL_PIN_TYPE_UNSPEC, 0 },
337 };
338
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
next prev parent reply other threads:[~2023-04-28 17:53 UTC|newest]
Thread overview: 149+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 0:20 [RFC PATCH v7 0/8] Create common DPLL configuration API Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-04-28 0:20 ` [RFC PATCH v7 1/8] dpll: spec: Add Netlink spec in YAML Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-05-04 12:02 ` Jiri Pirko
2023-05-04 12:02 ` Jiri Pirko
2023-05-04 21:24 ` Jakub Kicinski
2023-05-04 21:24 ` Jakub Kicinski
2023-05-05 10:29 ` Jiri Pirko
2023-05-05 10:29 ` Jiri Pirko
2023-05-11 7:44 ` Kubalewski, Arkadiusz
2023-05-11 8:00 ` Jiri Pirko
2023-05-11 14:55 ` Jakub Kicinski
2023-05-11 7:40 ` Kubalewski, Arkadiusz
2023-05-11 7:59 ` Jiri Pirko
2023-05-11 20:51 ` Kubalewski, Arkadiusz
2023-05-15 9:30 ` Jiri Pirko
2023-05-15 9:30 ` Jiri Pirko
2023-05-16 12:05 ` Kubalewski, Arkadiusz
2023-05-16 12:05 ` Kubalewski, Arkadiusz
2023-05-16 14:33 ` Jiri Pirko
2023-05-16 14:33 ` Jiri Pirko
2023-05-18 13:24 ` Kubalewski, Arkadiusz
2023-05-18 13:24 ` Kubalewski, Arkadiusz
2023-05-18 14:02 ` Jiri Pirko
2023-05-18 14:02 ` Jiri Pirko
2023-05-11 15:20 ` Jakub Kicinski
2023-05-11 20:53 ` Kubalewski, Arkadiusz
2023-05-11 23:29 ` Jakub Kicinski
2023-05-16 12:15 ` Kubalewski, Arkadiusz
2023-05-16 12:15 ` Kubalewski, Arkadiusz
2023-05-11 7:38 ` Kubalewski, Arkadiusz
2023-05-11 8:14 ` Jiri Pirko
2023-05-11 20:53 ` Kubalewski, Arkadiusz
2023-05-11 15:26 ` Jakub Kicinski
2023-05-11 20:54 ` Kubalewski, Arkadiusz
2023-04-28 0:20 ` [RFC PATCH v7 2/8] dpll: Add DPLL framework base functions Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-05-02 15:38 ` Jiri Pirko
2023-05-02 15:38 ` Jiri Pirko
2023-06-06 18:47 ` Kubalewski, Arkadiusz
2023-06-06 18:47 ` Kubalewski, Arkadiusz
2023-05-03 8:09 ` Jiri Pirko
2023-05-03 8:09 ` Jiri Pirko
2023-06-06 18:50 ` Kubalewski, Arkadiusz
2023-06-06 18:50 ` Kubalewski, Arkadiusz
2023-05-04 11:18 ` Jiri Pirko
2023-05-04 11:18 ` Jiri Pirko
2023-05-04 20:27 ` Jakub Kicinski
2023-05-04 20:27 ` Jakub Kicinski
2023-06-06 18:55 ` Kubalewski, Arkadiusz
2023-06-06 18:55 ` Kubalewski, Arkadiusz
2023-05-04 21:21 ` Jakub Kicinski
2023-05-04 21:21 ` Jakub Kicinski
2023-06-09 12:54 ` Kubalewski, Arkadiusz
2023-06-09 12:54 ` Kubalewski, Arkadiusz
2023-05-09 13:40 ` Jiri Pirko
2023-06-09 12:53 ` Kubalewski, Arkadiusz
2023-06-09 12:53 ` Kubalewski, Arkadiusz
2023-06-13 13:49 ` Jiri Pirko
2023-06-13 13:49 ` Jiri Pirko
2023-05-22 14:45 ` Paolo Abeni
2023-05-22 14:45 ` Paolo Abeni
2023-06-09 12:51 ` Kubalewski, Arkadiusz
2023-06-09 12:51 ` Kubalewski, Arkadiusz
2023-04-28 0:20 ` [RFC PATCH v7 3/8] dpll: documentation on DPLL subsystem interface Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-05-02 7:50 ` kernel test robot
2023-05-04 19:04 ` Jakub Kicinski
2023-05-04 19:04 ` Jakub Kicinski
2023-05-05 13:16 ` Vadim Fedorenko
2023-05-05 13:16 ` Vadim Fedorenko
2023-05-05 15:29 ` Jakub Kicinski
2023-05-05 15:29 ` Jakub Kicinski
2023-05-11 10:23 ` Kubalewski, Arkadiusz
2023-04-28 0:20 ` [RFC PATCH v7 4/8] ice: add admin commands to access cgu configuration Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-04-28 3:20 ` kernel test robot
2023-04-28 17:53 ` kernel test robot [this message]
2023-04-28 0:20 ` [RFC PATCH v7 5/8] ice: implement dpll interface to control cgu Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-04-28 6:05 ` kernel test robot
2023-04-28 8:18 ` kernel test robot
2023-05-03 12:18 ` Jiri Pirko
2023-05-03 12:18 ` Jiri Pirko
2023-05-15 22:07 ` Kubalewski, Arkadiusz
2023-05-15 22:07 ` Kubalewski, Arkadiusz
2023-05-16 6:26 ` Jiri Pirko
2023-05-16 6:26 ` Jiri Pirko
2023-05-18 16:06 ` Kubalewski, Arkadiusz
2023-05-18 16:06 ` Kubalewski, Arkadiusz
2023-05-19 6:15 ` Jiri Pirko
2023-05-19 6:15 ` Jiri Pirko
2023-05-25 9:01 ` Kubalewski, Arkadiusz
2023-05-25 9:01 ` Kubalewski, Arkadiusz
2023-05-19 6:47 ` Paolo Abeni
2023-05-19 6:47 ` Paolo Abeni
2023-05-25 9:05 ` Kubalewski, Arkadiusz
2023-05-25 9:05 ` Kubalewski, Arkadiusz
2023-05-15 17:12 ` Jiri Pirko
2023-05-15 17:12 ` Jiri Pirko
2023-05-16 9:22 ` Kubalewski, Arkadiusz
2023-05-16 9:22 ` Kubalewski, Arkadiusz
2023-05-16 11:46 ` Jiri Pirko
2023-05-16 11:46 ` Jiri Pirko
2023-05-18 16:07 ` Kubalewski, Arkadiusz
2023-05-18 16:07 ` Kubalewski, Arkadiusz
2023-05-19 6:15 ` Jiri Pirko
2023-05-19 6:15 ` Jiri Pirko
2023-04-28 0:20 ` [RFC PATCH v7 6/8] ptp_ocp: implement DPLL ops Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-04-28 6:36 ` kernel test robot
2023-05-04 9:27 ` Jiri Pirko
2023-05-04 9:27 ` Jiri Pirko
2023-05-05 13:43 ` Vadim Fedorenko
2023-05-05 13:43 ` Vadim Fedorenko
2023-05-06 12:42 ` Jiri Pirko
2023-05-06 12:42 ` Jiri Pirko
2023-04-28 0:20 ` [RFC PATCH v7 7/8] netdev: expose DPLL pin handle for netdevice Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-04-28 2:36 ` Stephen Hemminger
2023-04-28 2:36 ` Stephen Hemminger
2023-04-28 10:00 ` Vadim Fedorenko
2023-04-28 10:00 ` Vadim Fedorenko
2023-04-28 2:49 ` kernel test robot
2023-04-28 3:09 ` kernel test robot
2023-05-04 20:31 ` Jakub Kicinski
2023-05-04 20:31 ` Jakub Kicinski
2023-05-05 10:32 ` Jiri Pirko
2023-05-05 10:32 ` Jiri Pirko
2023-04-28 0:20 ` [RFC PATCH v7 8/8] mlx5: Implement SyncE support using DPLL infrastructure Vadim Fedorenko
2023-04-28 0:20 ` Vadim Fedorenko
2023-05-02 8:55 ` [RFC PATCH v7 0/8] Create common DPLL configuration API Jiri Pirko
2023-05-02 8:55 ` Jiri Pirko
2023-05-02 13:04 ` Jiri Pirko
2023-05-02 13:04 ` Jiri Pirko
2023-05-25 12:52 ` Kubalewski, Arkadiusz
2023-05-25 12:52 ` Kubalewski, Arkadiusz
2023-05-11 7:52 ` Jiri Pirko
2023-05-25 13:01 ` Kubalewski, Arkadiusz
2023-05-25 13:01 ` Kubalewski, Arkadiusz
2023-05-17 10:18 ` Jiri Pirko
2023-05-17 10:18 ` Jiri Pirko
2023-05-26 10:14 ` Kubalewski, Arkadiusz
2023-05-26 10:14 ` Kubalewski, Arkadiusz
2023-05-26 10:39 ` Jiri Pirko
2023-05-26 10:39 ` Jiri Pirko
2023-06-05 10:07 ` Kubalewski, Arkadiusz
2023-06-05 10:07 ` Kubalewski, Arkadiusz
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