From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>
Subject: Re: [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable from CDAT
Date: Fri, 12 May 2023 15:33:23 +0100 [thread overview]
Message-ID: <20230512153323.00000d7b@Huawei.com> (raw)
In-Reply-To: <168357882541.2756219.12547742982939088156.stgit@djiang5-mobl3>
On Mon, 08 May 2023 13:47:05 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Provide a callback to parse the Device Scoped Latency and Bandwidth
> Information Structure (DSLBIS) in the CDAT structures. The DSLBIS
> contains the bandwidth and latency information that's tied to a DSMAS
> handle. The driver will retrieve the read and write latency and
> bandwidth associated with the DSMAS which is tied to a DPA range.
>
> Coherent Device Attribute Table 1.03 2.1 Device Scoped Latency and
> Bandwidth Information Structure (DSLBIS)
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
A few trivial suggestions inline. Change them if you like. I don't mind that much.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> v5:
> - Remove macro for common headers. (Jonathan)
> - Use acpi_table_parse_cdat().
> - Remove unlikely(). (Dan)
> v3:
> - Added spec section in commit header. (Alison)
> - Remove void * recast. (Alison)
> - Rework comment. (Alison)
> - Move CDAT parse to cxl_endpoint_port_probe()
> - Convert to use 'struct node_hmem_attrs'
>
> v2:
> - Add size check to DSLIBIS table. (Lukas)
> - Remove unnecessary entry type check. (Jonathan)
> - Move data_type check to after match. (Jonathan)
> - Skip unknown data type. (Jonathan)
> - Add overflow check for unit multiply. (Jonathan)
> - Use dev_warn() when entries parsing fail. (Jonathan)
> ---
> drivers/cxl/core/cdat.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++-
> drivers/cxl/cxl.h | 2 +
> 2 files changed, 90 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index 61979f0789aa..6e14d04c0453 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /* Copyright(c) 2023 Intel Corporation. All rights reserved. */
> #include <linux/acpi.h>
> +#include <linux/overflow.h>
> #include "cxlpci.h"
> #include "cxl.h"
>
> @@ -32,9 +33,94 @@ static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg,
> return 0;
> }
>
> +static void cxl_access_coordinate_set(struct access_coordinate *coord,
> + int access, unsigned int val)
> +{
> + switch (access) {
> + case ACPI_HMAT_ACCESS_LATENCY:
> + coord->read_latency = val;
> + coord->write_latency = val;
> + break;
> + case ACPI_HMAT_READ_LATENCY:
> + coord->read_latency = val;
> + break;
> + case ACPI_HMAT_WRITE_LATENCY:
> + coord->write_latency = val;
> + break;
> + case ACPI_HMAT_ACCESS_BANDWIDTH:
> + coord->read_bandwidth = val;
> + coord->write_bandwidth = val;
> + break;
> + case ACPI_HMAT_READ_BANDWIDTH:
> + coord->read_bandwidth = val;
> + break;
> + case ACPI_HMAT_WRITE_BANDWIDTH:
> + coord->write_bandwidth = val;
> + break;
> + }
> +}
> +
> +static int cdat_dslbis_handler(union acpi_subtable_headers *header, void *arg,
> + const unsigned long end)
> +{
> + struct acpi_cdat_dslbis *dslbis = (struct acpi_cdat_dslbis *)header;
As for DSMAS, cast from the more obviously appropriate &header->cdat
> + struct list_head *dsmas_list = arg;
> + struct dsmas_entry *dent;
> + u16 len;
> +
> + len = le16_to_cpu((__force __le16)dslbis->header.length);
> + if (len != sizeof(*dslbis) || (unsigned long)header + len > end) {
> + pr_warn("Malformed DSLBIS table length: (%lu:%u)\n",
> + (unsigned long)sizeof(*dslbis), len);
> + return -EINVAL;
> + }
> +
> + /* Skip unrecognized data type */
> + if (dslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH)
> + return 0;
> +
> + list_for_each_entry(dent, dsmas_list, list) {
> + u64 val;
> + int rc;
> +
> + if (dslbis->handle != dent->handle)
> + continue;
> +
> + /* Not a memory type, skip */
> + if ((dslbis->flags & ACPI_HMAT_MEMORY_HIERARCHY) !=
> + ACPI_HMAT_MEMORY)
> + return 0;
> +
> + rc = check_mul_overflow(le64_to_cpu((__force __le64)dslbis->entry_base_unit),
> + le16_to_cpu((__force __le16)dslbis->entry[0]), &val);
> + if (rc)
> + pr_warn("DSLBIS value overflowed.\n");
> +
> + cxl_access_coordinate_set(&dent->coord, dslbis->data_type, val);
> + break;
> + }
> +
> + return 0;
> +}
> +
> int cxl_cdat_endpoint_process(struct cxl_port *port, struct list_head *list)
> {
> - return acpi_table_parse_cdat(ACPI_CDAT_TYPE_DSMAS, cdat_dsmas_handler,
> - list, port->cdat.table);
> + int rc;
> +
> + rc = acpi_table_parse_cdat(ACPI_CDAT_TYPE_DSMAS, cdat_dsmas_handler,
> + list, port->cdat.table);
> + if (rc <= 0) {
> + if (rc == 0)
> + rc = -ENOENT;
> + return rc;
> + }
if (rc < 0)
return rc;
if (rc == 0)
return -ENOENT;
is a tiny bit simpler.
> +
> + rc = acpi_table_parse_cdat(ACPI_CDAT_TYPE_DSLBIS,
> + cdat_dslbis_handler,
> + list, port->cdat.table);
> + if (rc == 0)
> + rc = -ENOENT;
I'd burn a few lines of code for readability rather than fudging the
return value.
if (rc < 0)
return rc;
if (rc == 0)
return -ENOENT;
return 0;
> +
> + return rc;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_cdat_endpoint_process, CXL);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index dda7238b47f5..ca3d0d74f2e5 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -8,6 +8,7 @@
> #include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/list.h>
> +#include <linux/node.h>
> #include <linux/log2.h>
> #include <linux/io.h>
>
> @@ -797,6 +798,7 @@ struct dsmas_entry {
> struct list_head list;
> struct range dpa_range;
> u8 handle;
> + struct access_coordinate coord;
> };
>
> #ifdef CONFIG_ACPI
>
>
next prev parent reply other threads:[~2023-05-12 14:33 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 20:46 [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-08 20:46 ` [PATCH v5 01/14] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-12 14:26 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-12 14:33 ` Jonathan Cameron [this message]
2023-05-08 20:47 ` [PATCH v5 03/14] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-12 14:41 ` Jonathan Cameron
2023-05-16 17:49 ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 04/14] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-12 14:50 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 05/14] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-08 20:47 ` [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-05-12 14:59 ` Jonathan Cameron
2023-05-16 20:58 ` Dave Jiang
2023-05-16 21:13 ` Dan Williams
2023-05-16 21:52 ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-12 15:05 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 08/14] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-12 15:09 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 09/14] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-05-12 15:16 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 10/14] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-05-12 15:17 ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 11/14] cxl: Move read_cdat_data() to after media is ready Dave Jiang
2023-05-12 15:18 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 12/14] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-05-12 15:30 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-05-12 15:33 ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-05-12 15:36 ` Jonathan Cameron
2023-05-17 22:28 ` Dave Jiang
2023-05-12 15:28 ` [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-05-16 21:49 ` Dan Williams
2023-05-17 8:50 ` Jonathan Cameron
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