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From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: linux-cxl@vger.kernel.org, dan.j.williams@intel.com,
	ira.weiny@intel.com, vishal.l.verma@intel.com,
	alison.schofield@intel.com
Subject: Re: [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports
Date: Tue, 16 May 2023 13:58:47 -0700	[thread overview]
Message-ID: <4f398988-e5fa-cbc8-f73a-bfefaf89e252@intel.com> (raw)
In-Reply-To: <20230512155957.00000c2f@Huawei.com>



On 5/12/23 7:59 AM, Jonathan Cameron wrote:
> On Mon, 08 May 2023 13:47:29 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
> 
>> Each CXL host bridge is represented by an ACPI0016 device. A generic port
>> device handle that is an ACPI device is represented by a string of
>> ACPI0016 device HID and UID. Create a device handle from the ACPI device
>> and retrieve the access coordinates from the stored memory targets. The
>> access coordinates are stored under the cxl_dport that is associated with
>> the CXL host bridge.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>   drivers/cxl/acpi.c |   28 ++++++++++++++++++++++++++++
>>   drivers/cxl/cxl.h  |    2 ++
>>   2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
>> index f9b35e8fe810..675a4f423f4b 100644
>> --- a/drivers/cxl/acpi.c
>> +++ b/drivers/cxl/acpi.c
>> @@ -537,8 +537,26 @@ static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
>>   	return 0;
>>   }
>>   
>> +static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
>> +{
>> +	struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
>> +	u8 handle[ACPI_SRAT_DEVICE_HANDLE_SIZE] = { 0 };
>> +	int rc;
>> +
>> +	/* ACPI spec 6.5 tABLE 5.65 */
> 
> tABLE?

ooops caps lock

> 
>> +	memcpy(handle, acpi_device_hid(hb), 8);
>> +	memcpy(&handle[8], acpi_device_uid(hb), 4);
>> +
>> +	rc = acpi_get_genport_coordinates(handle, dport->genport_coord);
>> +	if (rc)
>> +		return rc;
>> +
>> +	return 0;
>> +}
>> +
>>   static int add_host_bridge_dport(struct device *match, void *arg)
>>   {
>> +	int ret;
>>   	acpi_status rc;
>>   	struct device *bridge;
>>   	unsigned long long uid;
>> @@ -594,6 +612,16 @@ static int add_host_bridge_dport(struct device *match, void *arg)
>>   	if (IS_ERR(dport))
>>   		return PTR_ERR(dport);
>>   
>> +	dport->genport_coord = devm_kzalloc(dport->dport,
>> +					    sizeof(*dport->genport_coord),
>> +					    GFP_KERNEL);
> 
> It's pretty small - worth allocating separately?
> 
> Maybe add something on why to the patch description if there is another reason
> for this dance.

My intention was to allow detection of whether the data exists or not 
based on if the ptr is NULL. I'll add explanation in patch description.

> 
>> +	if (!dport->genport_coord)
>> +		return -ENOMEM;
>> +
>> +	ret = get_genport_coordinates(match, dport);
>> +	if (ret)
>> +		dev_dbg(match, "Failed to get generic port perf coordinates.\n");
>> +
>>   	return 0;
>>   }
>>   
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index c1e2c3703a63..033b822a20f2 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -626,6 +626,7 @@ cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
>>    * @rcrb: base address for the Root Complex Register Block
>>    * @rch: Indicate whether this dport was enumerated in RCH or VH mode
>>    * @port: reference to cxl_port that contains this downstream port
>> + * @genport_coord: access coordinates (performance) from ACPI generic port
>>    * @coord: access coordinates (performance) for switch from CDAT
>>    * @link_latency: calculated PCIe downstream latency
>>    */
>> @@ -636,6 +637,7 @@ struct cxl_dport {
>>   	resource_size_t rcrb;
>>   	bool rch;
>>   	struct cxl_port *port;
>> +	struct access_coordinate *genport_coord;
>>   	struct access_coordinate coord;
>>   	long link_latency;
>>   };
>>
>>
> 

  reply	other threads:[~2023-05-16 20:58 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-08 20:46 [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-08 20:46 ` [PATCH v5 01/14] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-12 14:26   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 02/14] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-12 14:33   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 03/14] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-12 14:41   ` Jonathan Cameron
2023-05-16 17:49     ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 04/14] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-12 14:50   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 05/14] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-08 20:47 ` [PATCH v5 06/14] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-05-12 14:59   ` Jonathan Cameron
2023-05-16 20:58     ` Dave Jiang [this message]
2023-05-16 21:13       ` Dan Williams
2023-05-16 21:52         ` Dave Jiang
2023-05-08 20:47 ` [PATCH v5 07/14] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-12 15:05   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 08/14] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-12 15:09   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 09/14] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-05-12 15:16   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 10/14] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-05-12 15:17   ` Jonathan Cameron
2023-05-08 20:47 ` [PATCH v5 11/14] cxl: Move read_cdat_data() to after media is ready Dave Jiang
2023-05-12 15:18   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 12/14] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-05-12 15:30   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 13/14] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-05-12 15:33   ` Jonathan Cameron
2023-05-08 20:48 ` [PATCH v5 14/14] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-05-12 15:36   ` Jonathan Cameron
2023-05-17 22:28     ` Dave Jiang
2023-05-12 15:28 ` [PATCH v5 00/14] cxl: Add support for QTG ID retrieval for CXL subsystem Jonathan Cameron
2023-05-16 21:49   ` Dan Williams
2023-05-17  8:50     ` Jonathan Cameron

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