[avpatel:riscv_timer_imp_v1 3/35] drivers/crypto/hisilicon/qm.c:621:9: warning: ISO C90 forbids mixed declarations and code

[avpatel:riscv_timer_imp_v1 3/35] drivers/crypto/hisilicon/qm.c:621:9: warning: ISO C90 forbids mixed declarations and code

[kernel test robot]

tree:   https://github.com/avpatel/linux.git riscv_timer_imp_v1
head:   32160e9f14930198623931dcab8fca27eea7b641
commit: 1c5afb87ad4f39d46b632a0b5f32763d7ebac95f [3/35] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20230512/202305122158.88fFu8uv-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/avpatel/linux/commit/1c5afb87ad4f39d46b632a0b5f32763d7ebac95f
        git remote add avpatel https://github.com/avpatel/linux.git
        git fetch --no-tags avpatel riscv_timer_imp_v1
        git checkout 1c5afb87ad4f39d46b632a0b5f32763d7ebac95f
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/crypto/hisilicon/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305122158.88fFu8uv-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/crypto/hisilicon/qm.c: In function 'qm_mb_write':
>> drivers/crypto/hisilicon/qm.c:621:9: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
     621 |         unsigned long tmp0 = 0, tmp1 = 0;
         |         ^~~~~~~~


vim +621 drivers/crypto/hisilicon/qm.c

   608	
   609	/* 128 bit should be written to hardware at one time to trigger a mailbox */
   610	static void qm_mb_write(struct hisi_qm *qm, const void *src)
   611	{
   612		void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
   613	
   614		if (!IS_ENABLED(CONFIG_ARM64)) {
   615			memcpy_toio(fun_base, src, 16);
   616			dma_wmb();
   617			return;
   618		}
   619	
   620	#if IS_ENABLED(CONFIG_ARM64)
 > 621		unsigned long tmp0 = 0, tmp1 = 0;
   622	
   623		asm volatile("ldp %0, %1, %3\n"
   624			     "stp %0, %1, %2\n"
   625			     "dmb oshst\n"
   626			     : "=&r" (tmp0),
   627			       "=&r" (tmp1),
   628			       "+Q" (*((char __iomem *)fun_base))
   629			     : "Q" (*((char *)src))
   630			     : "memory");
   631	#endif
   632	

-- 
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https://github.com/intel/lkp-tests