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From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>
Cc: Samuel Holland <samuel@sholland.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v3 05/10] riscv: add the Bouffalolab SoC family Kconfig option
Date: Mon, 15 May 2023 00:56:46 +0800	[thread overview]
Message-ID: <20230514165651.2199-6-jszhang@kernel.org> (raw)
In-Reply-To: <20230514165651.2199-1-jszhang@kernel.org>

The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and
LP. The D0 is 64bit RISC-V GC compatible, so can run linux.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..33220b5144bb 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,10 @@
 menu "SoC selection"
 
+config ARCH_BOUFFALOLAB
+	bool "Bouffalolab SoCs"
+	help
+	  This enables support for Bouffalolab SoC platforms.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool SOC_MICROCHIP_POLARFIRE
 
-- 
2.40.0


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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>
Cc: Samuel Holland <samuel@sholland.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v3 05/10] riscv: add the Bouffalolab SoC family Kconfig option
Date: Mon, 15 May 2023 00:56:46 +0800	[thread overview]
Message-ID: <20230514165651.2199-6-jszhang@kernel.org> (raw)
In-Reply-To: <20230514165651.2199-1-jszhang@kernel.org>

The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and
LP. The D0 is 64bit RISC-V GC compatible, so can run linux.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..33220b5144bb 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,10 @@
 menu "SoC selection"
 
+config ARCH_BOUFFALOLAB
+	bool "Bouffalolab SoCs"
+	help
+	  This enables support for Bouffalolab SoC platforms.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool SOC_MICROCHIP_POLARFIRE
 
-- 
2.40.0


  parent reply	other threads:[~2023-05-14 17:08 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-14 16:56 [PATCH v3 00/10] riscv: add Bouffalolab bl808 support Jisheng Zhang
2023-05-14 16:56 ` Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 01/10] dt-bindings: vendor-prefixes: add bouffalolab Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 02/10] dt-bindings: interrupt-controller: Add bouffalolab bl808 plic Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 18:33   ` Conor Dooley
2023-05-14 18:33     ` Conor Dooley
2023-05-14 16:56 ` [PATCH v3 03/10] dt-bindings: serial: add documentation for Bouffalolab UART Driver Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 18:17   ` Conor Dooley
2023-05-14 18:17     ` Conor Dooley
2023-05-14 23:28     ` Jisheng Zhang
2023-05-14 23:28       ` Jisheng Zhang
2023-05-15 16:58       ` Conor Dooley
2023-05-15 16:58         ` Conor Dooley
2023-05-15  6:24   ` Krzysztof Kozlowski
2023-05-15  6:24     ` Krzysztof Kozlowski
2023-05-14 16:56 ` [PATCH v3 04/10] serial: bflb_uart: add " Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 19:25   ` kernel test robot
2023-05-14 19:25     ` kernel test robot
2023-05-14 23:30     ` Jisheng Zhang
2023-05-14 23:30       ` Jisheng Zhang
2023-05-14 16:56 ` Jisheng Zhang [this message]
2023-05-14 16:56   ` [PATCH v3 05/10] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 06/10] dt-bindings: riscv: Add bouffalolab bl808 board compatibles Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 18:39   ` Conor Dooley
2023-05-14 18:39     ` Conor Dooley
2023-05-18 15:59     ` Jisheng Zhang
2023-05-18 15:59       ` Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 07/10] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 08/10] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 09/10] MAINTAINERS: riscv: add entry for Bouffalolab SoC Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang
2023-05-14 16:56 ` [PATCH v3 10/10] riscv: defconfig: enable BOUFFALOLAB SoC Jisheng Zhang
2023-05-14 16:56   ` Jisheng Zhang

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