[PATCH 0/2] Fix SM8550 LLCC

[PATCH 0/2] Fix SM8550 LLCC

[Konrad Dybcio]

LLCC was recently untangled as far as register regions go [1], but
SM8550 was omitted. Fix it.

[1] https://lore.kernel.org/all/20230314080443.64635-1-manivannan.sadhasivam@linaro.org/

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (2):
      dt-bindings: cache: qcom,llcc: Fix SM8550 description
      arm64: dts: qcom: sm8550: Use the correct LLCC register scheme

 Documentation/devicetree/bindings/cache/qcom,llcc.yaml |  1 +
 arch/arm64/boot/dts/qcom/sm8550.dtsi                   | 11 +++++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)
---
base-commit: 885df05bf634d589fbf030c3751614eaa453fb5d
change-id: 20230517-topic-kailua-llcc-ef16d72b1cfe

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description

[Konrad Dybcio]

SM8550 (LLCCv4.1) has 4 register regions, this was not described
between its addition and the restructurization that happened in
the commit referenced in the fixes tag.

Fix it.

Fixes: 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index d8b91944180a..44892aa589fd 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -129,6 +129,7 @@ allOf:
               - qcom,sm8250-llcc
               - qcom,sm8350-llcc
               - qcom,sm8450-llcc
+              - qcom,sm8550-llcc
     then:
       properties:
         reg:

-- 
2.40.1

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description

[Manivannan Sadhasivam]

On Wed, May 17, 2023 at 04:18:49AM +0200, Konrad Dybcio wrote:
> SM8550 (LLCCv4.1) has 4 register regions, this was not described
> between its addition and the restructurization that happened in
> the commit referenced in the fixes tag.
> 
> Fix it.
> 
> Fixes: 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks")

I'm not sure if the Fixes tag should point to the patch adding SM8550 support or
the restructuring patch.

> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

But the change LGTM!

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> ---
>  Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> index d8b91944180a..44892aa589fd 100644
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> @@ -129,6 +129,7 @@ allOf:
>                - qcom,sm8250-llcc
>                - qcom,sm8350-llcc
>                - qcom,sm8450-llcc
> +              - qcom,sm8550-llcc
>      then:
>        properties:
>          reg:
> 
> -- 
> 2.40.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description

[Konrad Dybcio]

On 17.05.2023 07:44, Manivannan Sadhasivam wrote:
> On Wed, May 17, 2023 at 04:18:49AM +0200, Konrad Dybcio wrote:
>> SM8550 (LLCCv4.1) has 4 register regions, this was not described
>> between its addition and the restructurization that happened in
>> the commit referenced in the fixes tag.
>>
>> Fix it.
>>
>> Fixes: 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks")
> 
> I'm not sure if the Fixes tag should point to the patch adding SM8550 support or
> the restructuring patch.
Right.. I wanted to add *some* fixes tag (clearly a bugfix)
and decided this one (and the one in patch 2) were the least bad
options, as the cleanup landed after/parallel to 8550 introduction.

Konrad
> 
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> But the change LGTM!
> 
> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
> 
> - Mani
> 
>> ---
>>  Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> index d8b91944180a..44892aa589fd 100644
>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> @@ -129,6 +129,7 @@ allOf:
>>                - qcom,sm8250-llcc
>>                - qcom,sm8350-llcc
>>                - qcom,sm8450-llcc
>> +              - qcom,sm8550-llcc
>>      then:
>>        properties:
>>          reg:
>>
>> -- 
>> 2.40.1
>>
> 

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description

[Krzysztof Kozlowski]

On Wed, 17 May 2023 04:18:49 +0200, Konrad Dybcio wrote:
> SM8550 (LLCCv4.1) has 4 register regions, this was not described
> between its addition and the restructurization that happened in
> the commit referenced in the fixes tag.
> 
> Fix it.
> 
> Fixes: 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1782401


system-cache-controller@25000000: reg: [[0, 620756992, 0, 8388608], [0, 629145600, 0, 2097152]] is too short
	arch/arm64/boot/dts/qcom/sm8550-mtp.dtb
	arch/arm64/boot/dts/qcom/sm8550-qrd.dtb

system-cache-controller@25000000: reg-names:0: 'llcc0_base' was expected
	arch/arm64/boot/dts/qcom/sm8550-mtp.dtb
	arch/arm64/boot/dts/qcom/sm8550-qrd.dtb

system-cache-controller@25000000: reg-names:1: 'llcc1_base' was expected
	arch/arm64/boot/dts/qcom/sm8550-mtp.dtb
	arch/arm64/boot/dts/qcom/sm8550-qrd.dtb

system-cache-controller@25000000: reg-names: ['llcc_base', 'llcc_broadcast_base'] is too short
	arch/arm64/boot/dts/qcom/sm8550-mtp.dtb
	arch/arm64/boot/dts/qcom/sm8550-qrd.dtb

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description

[Krzysztof Kozlowski]

On 17/05/2023 04:18, Konrad Dybcio wrote:
> SM8550 (LLCCv4.1) has 4 register regions, this was not described
> between its addition and the restructurization that happened in
> the commit referenced in the fixes tag.
> 
> Fix it.
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 2/2] arm64: dts: qcom: sm8550: Use the correct LLCC register scheme

[Konrad Dybcio]

During the ABI-breaking (for good reasons) conversion of the LLCC
register description, SM8550 was not taken into account, resulting
in LLCC being broken on any kernel containing the patch referenced
in the fixes tag.

Fix it by describing the regions properly.

Fixes: ee13b5008707 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 6e9bad8f6f33..70ae7e2e900a 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3762,9 +3762,16 @@ gem_noc: interconnect@24100000 {
 
 		system-cache-controller@25000000 {
 			compatible = "qcom,sm8550-llcc";
-			reg = <0 0x25000000 0 0x800000>,
+			reg = <0 0x25000000 0 0x200000>,
+			      <0 0x25200000 0 0x200000>,
+			      <0 0x25400000 0 0x200000>,
+			      <0 0x25600000 0 0x200000>,
 			      <0 0x25800000 0 0x200000>;
-			reg-names = "llcc_base", "llcc_broadcast_base";
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc2_base",
+				    "llcc3_base",
+				    "llcc_broadcast_base";
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 

-- 
2.40.1

Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Use the correct LLCC register scheme

[Manivannan Sadhasivam]

On Wed, May 17, 2023 at 04:18:50AM +0200, Konrad Dybcio wrote:
> During the ABI-breaking (for good reasons) conversion of the LLCC
> register description, SM8550 was not taken into account, resulting
> in LLCC being broken on any kernel containing the patch referenced
> in the fixes tag.
> 
> Fix it by describing the regions properly.
> 
> Fixes: ee13b5008707 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks")

Same comment about the Fixes tag.

> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

I do not have access to the SM8550 documentation to confirm the base address but
I hope that it has been taken care of.

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 6e9bad8f6f33..70ae7e2e900a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3762,9 +3762,16 @@ gem_noc: interconnect@24100000 {
>  
>  		system-cache-controller@25000000 {
>  			compatible = "qcom,sm8550-llcc";
> -			reg = <0 0x25000000 0 0x800000>,
> +			reg = <0 0x25000000 0 0x200000>,
> +			      <0 0x25200000 0 0x200000>,
> +			      <0 0x25400000 0 0x200000>,
> +			      <0 0x25600000 0 0x200000>,
>  			      <0 0x25800000 0 0x200000>;
> -			reg-names = "llcc_base", "llcc_broadcast_base";
> +			reg-names = "llcc0_base",
> +				    "llcc1_base",
> +				    "llcc2_base",
> +				    "llcc3_base",
> +				    "llcc_broadcast_base";
>  			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> 
> -- 
> 2.40.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: (subset) [PATCH 0/2] Fix SM8550 LLCC

[Bjorn Andersson]

On Wed, 17 May 2023 04:18:48 +0200, Konrad Dybcio wrote:
> LLCC was recently untangled as far as register regions go [1], but
> SM8550 was omitted. Fix it.
> 
> [1] https://lore.kernel.org/all/20230314080443.64635-1-manivannan.sadhasivam@linaro.org/
> 
> 

Applied, thanks!

[2/2] arm64: dts: qcom: sm8550: Use the correct LLCC register scheme
      commit: 661a4f089317c877aecd598fb70cd46510cc8d29

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>