* [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton.
@ 2023-05-31 16:55 Jingbo Wu
2023-05-31 16:55 ` [PATCH 1/2] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Jingbo Wu
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jingbo Wu @ 2023-05-31 16:55 UTC (permalink / raw)
To: clg, peter.maydell; +Cc: qemu-arm, qemu-devel, Felix Wu
From: Felix Wu <flwu@google.com>
Felix Wu (2):
hw/gpio: Add property for ASPEED GPIO in 32 bits basis
tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
hw/gpio/aspeed_gpio.c | 56 ++++++++++++++++++
include/qapi/qmp/qdict.h | 1 +
qobject/qdict.c | 13 ++++
tests/qtest/aspeed_gpio-test.c | 105 ++++++++++++++++++++++++++++++---
4 files changed, 166 insertions(+), 9 deletions(-)
--
2.41.0.rc0.172.g3f132b7071-goog
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] hw/gpio: Add property for ASPEED GPIO in 32 bits basis
2023-05-31 16:55 [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Jingbo Wu
@ 2023-05-31 16:55 ` Jingbo Wu
2023-05-31 16:55 ` [PATCH 2/2] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Jingbo Wu
2023-06-01 8:21 ` [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Cédric Le Goater
2 siblings, 0 replies; 4+ messages in thread
From: Jingbo Wu @ 2023-05-31 16:55 UTC (permalink / raw)
To: clg, peter.maydell; +Cc: qemu-arm, qemu-devel, Felix Wu
From: Felix Wu <flwu@google.com>
Added 32 bits property for ASPEED GPIO. Previously it can only be access in bitwise manner.
This change gives ASPEED similar behavior as Nuvoton.
Signed-off-by: Felix Wu <flwu@google.com>
---
hw/gpio/aspeed_gpio.c | 56 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 1e267dd482..e4fa5c1c79 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -951,6 +951,56 @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name,
aspeed_gpio_set_pin_level(s, set_idx, pin, level);
}
+static void aspeed_gpio_set_set(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ uint32_t set_val = 0;
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int set_idx = 0;
+
+ if (!visit_type_uint32(v, name, &set_val, errp)) {
+ return;
+ }
+
+ if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+
+ if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
+ error_setg(errp, "%s: invalid set_idx %s", __func__, name);
+ return;
+ }
+
+ aspeed_gpio_update(s, &s->sets[set_idx], set_val,
+ ~s->sets[set_idx].direction);
+}
+
+static void aspeed_gpio_get_set(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ uint32_t set_val = 0;
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int set_idx = 0;
+
+ if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+
+ if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
+ error_setg(errp, "%s: invalid set_idx %s", __func__, name);
+ return;
+ }
+
+ set_val = s->sets[set_idx].data_value;
+ visit_type_uint32(v, name, &set_val, errp);
+}
+
/****************** Setup functions ******************/
static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
[0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
@@ -1061,6 +1111,12 @@ static void aspeed_gpio_init(Object *obj)
g_free(name);
}
}
+
+ for (int i = 0; i < agc->nr_gpio_sets; i++) {
+ char *name = g_strdup_printf("gpio-set[%d]", i);
+ object_property_add(obj, name, "uint32", aspeed_gpio_get_set,
+ aspeed_gpio_set_set, NULL, NULL);
+ }
}
static const VMStateDescription vmstate_gpio_regs = {
--
2.41.0.rc0.172.g3f132b7071-goog
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
2023-05-31 16:55 [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Jingbo Wu
2023-05-31 16:55 ` [PATCH 1/2] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Jingbo Wu
@ 2023-05-31 16:55 ` Jingbo Wu
2023-06-01 8:21 ` [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Cédric Le Goater
2 siblings, 0 replies; 4+ messages in thread
From: Jingbo Wu @ 2023-05-31 16:55 UTC (permalink / raw)
To: clg, peter.maydell; +Cc: qemu-arm, qemu-devel, Felix Wu
From: Felix Wu <flwu@google.com>
- Added qtests to test gpio-set property for ASPEED.
- Added function to get uint in qdict.
Signed-off-by: Felix Wu <flwu@google.com>
---
include/qapi/qmp/qdict.h | 1 +
qobject/qdict.c | 13 ++++
tests/qtest/aspeed_gpio-test.c | 105 ++++++++++++++++++++++++++++++---
3 files changed, 110 insertions(+), 9 deletions(-)
diff --git a/include/qapi/qmp/qdict.h b/include/qapi/qmp/qdict.h
index 82e90fc072..50046f4285 100644
--- a/include/qapi/qmp/qdict.h
+++ b/include/qapi/qmp/qdict.h
@@ -57,6 +57,7 @@ void qdict_put_str(QDict *qdict, const char *key, const char *value);
double qdict_get_double(const QDict *qdict, const char *key);
int64_t qdict_get_int(const QDict *qdict, const char *key);
+uint64_t qdict_get_uint(const QDict *qdict, const char *key);
bool qdict_get_bool(const QDict *qdict, const char *key);
QList *qdict_get_qlist(const QDict *qdict, const char *key);
QDict *qdict_get_qdict(const QDict *qdict, const char *key);
diff --git a/qobject/qdict.c b/qobject/qdict.c
index 8faff230d3..916467958d 100644
--- a/qobject/qdict.c
+++ b/qobject/qdict.c
@@ -209,6 +209,19 @@ int64_t qdict_get_int(const QDict *qdict, const char *key)
return qnum_get_int(qobject_to(QNum, qdict_get(qdict, key)));
}
+/**
+ * qdict_get_uint(): Get an unsigned integer mapped by 'key'
+ *
+ * This function assumes that 'key' exists and it stores a
+ * QNum representable as uint.
+ *
+ * Return unsigned integer mapped by 'key'.
+ */
+uint64_t qdict_get_uint(const QDict *qdict, const char *key)
+{
+ return qnum_get_uint(qobject_to(QNum, qdict_get(qdict, key)));
+}
+
/**
* qdict_get_bool(): Get a bool mapped by 'key'
*
diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c
index d38f51d719..38000c7868 100644
--- a/tests/qtest/aspeed_gpio-test.c
+++ b/tests/qtest/aspeed_gpio-test.c
@@ -27,28 +27,115 @@
#include "qemu/timer.h"
#include "qapi/qmp/qdict.h"
#include "libqtest-single.h"
+#include "qemu/typedefs.h"
#define AST2600_GPIO_BASE 0x1E780000
#define GPIO_ABCD_DATA_VALUE 0x000
#define GPIO_ABCD_DIRECTION 0x004
+static uint32_t qtest_qom_get_uint32(QTestState *s, const char *path,
+ const char *property)
+{
+ QDict *r;
+
+ uint32_t res;
+ r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "
+ "{ 'path': %s, 'property': %s } }", path, property);
+ res = qdict_get_uint(r, "return");
+ qobject_unref(r);
+
+ return res;
+}
+
+static void qtest_qom_set_uint32(QTestState *s, const char *path,
+ const char *property, uint32_t value)
+{
+ QDict *r;
+
+ r = qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': "
+ "{ 'path': %s, 'property': %s, 'value': %" PRIu32 " } }",
+ path, property, value);
+ qobject_unref(r);
+}
+
+static const char *resp_get_error(QDict *r, const char* error_key)
+{
+ QDict *qdict;
+
+ g_assert(r);
+
+ qdict = qdict_get_qdict(r, "error");
+ if (qdict) {
+ return qdict_get_str(qdict, error_key);
+ }
+
+ return NULL;
+}
+
+static bool qtest_qom_check_error(QTestState *s, const char *path,
+ const char *property, const char *error_msg,
+ const char *error_msg_key)
+{
+ QDict *r;
+ bool b;
+
+ r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "
+ "{ 'path': %s, 'property': %s } }", path, property);
+ b = g_str_equal(resp_get_error(r, error_msg_key), error_msg);
+ qobject_unref(r);
+
+ return b;
+}
+
static void test_set_colocated_pins(const void *data)
{
QTestState *s = (QTestState *)data;
-
+ const char path[] = "/machine/soc/gpio";
/*
* gpioV4-7 occupy bits within a single 32-bit value, so we want to make
* sure that modifying one doesn't affect the other.
*/
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true);
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false);
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true);
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false);
- g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4"));
- g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5"));
- g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6"));
- g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7"));
+ qtest_qom_set_bool(s, path, "gpioV4", true);
+ qtest_qom_set_bool(s, path, "gpioV5", false);
+ qtest_qom_set_bool(s, path, "gpioV6", true);
+ qtest_qom_set_bool(s, path, "gpioV7", false);
+ g_assert(qtest_qom_get_bool(s, path, "gpioV4"));
+ g_assert(!qtest_qom_get_bool(s, path, "gpioV5"));
+ g_assert(qtest_qom_get_bool(s, path, "gpioV6"));
+ g_assert(!qtest_qom_get_bool(s, path, "gpioV7"));
+
+ /*
+ * Testing the gpio-set[%d] properties, using individual gpio boolean
+ * properties to do cross check.
+ * We use gpioR4-7 for test, Setting them to be 0b1010.
+ */
+ qtest_qom_set_uint32(s, path, "gpio-set[4]", 0x0);
+ g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") == 0x0);
+ qtest_qom_set_uint32(s, path, "gpio-set[4]", 0xa000);
+ g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") == 0xa000);
+
+ g_assert(!qtest_qom_get_bool(s, path, "gpioR4"));
+ g_assert(qtest_qom_get_bool(s, path, "gpioR5"));
+ g_assert(!qtest_qom_get_bool(s, path, "gpioR6"));
+ g_assert(qtest_qom_get_bool(s, path, "gpioR7"));
+
+ /*
+ * Testing the invalid indexing, the response info should contain following
+ * info:
+ * {key: "class", value: "GenericError"}
+ *
+ * For pins, it should follow "gpio%2[A-Z]%1d" or "gpio%3[18A-E]%1d" format.
+ */
+ const char error_msg[] = "GenericError";
+ const char error_msg_key [] = "class";
+
+ g_assert(qtest_qom_check_error(s, path, "gpioR+1", error_msg,
+ error_msg_key));
+ g_assert(qtest_qom_check_error(s, path, "gpio-set[99]", error_msg,
+ error_msg_key));
+ g_assert(qtest_qom_check_error(s, path, "gpio-set[-3]", error_msg,
+ error_msg_key));
}
static void test_set_input_pins(const void *data)
--
2.41.0.rc0.172.g3f132b7071-goog
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton.
2023-05-31 16:55 [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Jingbo Wu
2023-05-31 16:55 ` [PATCH 1/2] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Jingbo Wu
2023-05-31 16:55 ` [PATCH 2/2] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Jingbo Wu
@ 2023-06-01 8:21 ` Cédric Le Goater
2 siblings, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2023-06-01 8:21 UTC (permalink / raw)
To: Jingbo Wu, peter.maydell; +Cc: qemu-arm, qemu-devel, Andrew Jeffery
On 5/31/23 18:55, Jingbo Wu wrote:
> From: Felix Wu <flwu@google.com>
Hello Felix,
Thanks for the extension. It could be useful in some situations but
it seems also dangerous to set all lines controlled by a register
at once. The same comment applies to Nuvoton [1].
C.
[1] https://lore.kernel.org/qemu-devel/CAFEAcA-2_gwOUgapmgSSFGVNiOk9Grse_E3TVo=pQTf-OgW2vg@mail.gmail.com/
>
> Felix Wu (2):
> hw/gpio: Add property for ASPEED GPIO in 32 bits basis
> tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
>
> hw/gpio/aspeed_gpio.c | 56 ++++++++++++++++++
> include/qapi/qmp/qdict.h | 1 +
> qobject/qdict.c | 13 ++++
> tests/qtest/aspeed_gpio-test.c | 105 ++++++++++++++++++++++++++++++---
> 4 files changed, 166 insertions(+), 9 deletions(-)
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-06-01 8:22 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-31 16:55 [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Jingbo Wu
2023-05-31 16:55 ` [PATCH 1/2] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Jingbo Wu
2023-05-31 16:55 ` [PATCH 2/2] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Jingbo Wu
2023-06-01 8:21 ` [PATCH 0/2] Added 32 bits property for ASPEED GPIO with updated qtests. This change gives ASPEED GPIO similar behavior as Nuvoton Cédric Le Goater
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.