From: Frederic Barrat <fbarrat@linux.ibm.com>
To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 0/5] Various xive fixes
Date: Thu, 1 Jun 2023 14:13:26 +0200 [thread overview]
Message-ID: <20230601121331.487207-1-fbarrat@linux.ibm.com> (raw)
A set of small fixes for the interrupt controller (xive2) on P10.
Change log:
v2:
split last patch to do a bit of cleanup first
add Cedric's reviewed-by on the first 3 patches
Frederic Barrat (5):
pnv/xive2: Add definition for TCTXT Config register
pnv/xive2: Add definition for the ESB cache configuration register
pnv/xive2: Allow writes to the Physical Thread Enable registers
pnv/xive2: Introduce macros to manipulate TIMA addresses
pnv/xive2: Handle TIMA access through all ports
hw/intc/pnv_xive2.c | 20 +++++++++++++++++++-
hw/intc/pnv_xive2_regs.h | 8 ++++++++
hw/intc/xive.c | 16 ++++++++--------
include/hw/ppc/xive_regs.h | 16 ++++++++++++++++
4 files changed, 51 insertions(+), 9 deletions(-)
--
2.40.1
next reply other threads:[~2023-06-01 12:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-01 12:13 Frederic Barrat [this message]
2023-06-01 12:13 ` [PATCH v2 1/5] pnv/xive2: Add definition for TCTXT Config register Frederic Barrat
2023-06-01 12:13 ` [PATCH v2 2/5] pnv/xive2: Add definition for the ESB cache configuration register Frederic Barrat
2023-06-01 12:13 ` [PATCH v2 3/5] pnv/xive2: Allow writes to the Physical Thread Enable registers Frederic Barrat
2023-06-01 12:13 ` [PATCH v2 4/5] pnv/xive2: Introduce macros to manipulate TIMA addresses Frederic Barrat
2023-06-01 12:22 ` Cédric Le Goater
2023-06-01 12:13 ` [PATCH v2 5/5] pnv/xive2: Handle TIMA access through all ports Frederic Barrat
2023-06-01 12:25 ` Cédric Le Goater
2023-06-01 20:30 ` [PATCH v2 0/5] Various xive fixes Daniel Henrique Barboza
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