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From: Frederic Barrat <fbarrat@linux.ibm.com>
To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH v2 1/5] pnv/xive2: Add definition for TCTXT Config register
Date: Thu,  1 Jun 2023 14:13:27 +0200	[thread overview]
Message-ID: <20230601121331.487207-2-fbarrat@linux.ibm.com> (raw)
In-Reply-To: <20230601121331.487207-1-fbarrat@linux.ibm.com>

Add basic read/write support for the TCTXT Config register on P10. qemu
doesn't do anything with it yet, but it avoids logging a guest error
when skiboot configures the fused-core state:

qemu-system-ppc64 -machine powernv10 ... -d guest_errors
  ...
[    0.131670000,5] XIVE: [ IC 00  ] Initializing XIVE block ID 0...
XIVE[0] - TCTXT: invalid read @140
XIVE[0] - TCTXT: invalid write @140

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 hw/intc/pnv_xive2.c      | 8 +++++++-
 hw/intc/pnv_xive2_regs.h | 4 ++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index e688381536..f0817a124f 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1269,6 +1269,9 @@ static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset,
     case TCTXT_EN1_RESET:
         val = xive->tctxt_regs[TCTXT_EN1 >> 3];
         break;
+    case TCTXT_CFG:
+        val = xive->tctxt_regs[reg];
+        break;
     default:
         xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset);
     }
@@ -1280,6 +1283,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset,
                                      uint64_t val, unsigned size)
 {
     PnvXive2 *xive = PNV_XIVE2(opaque);
+    uint32_t reg = offset >> 3;
 
     switch (offset) {
     /*
@@ -1301,7 +1305,9 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset,
     case TCTXT_EN1_RESET:
         xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val;
         break;
-
+    case TCTXT_CFG:
+        xive->tctxt_regs[reg] = val;
+        break;
     default:
         xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset);
         return;
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
index 0c096e4adb..8f1e0a1fde 100644
--- a/hw/intc/pnv_xive2_regs.h
+++ b/hw/intc/pnv_xive2_regs.h
@@ -405,6 +405,10 @@
 #define X_TCTXT_EN1_RESET                       0x307
 #define TCTXT_EN1_RESET                         0x038
 
+/* TCTXT Config register */
+#define X_TCTXT_CFG                             0x328
+#define TCTXT_CFG                               0x140
+
 /*
  * VSD Tables
  */
-- 
2.40.1



  reply	other threads:[~2023-06-01 12:14 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-01 12:13 [PATCH v2 0/5] Various xive fixes Frederic Barrat
2023-06-01 12:13 ` Frederic Barrat [this message]
2023-06-01 12:13 ` [PATCH v2 2/5] pnv/xive2: Add definition for the ESB cache configuration register Frederic Barrat
2023-06-01 12:13 ` [PATCH v2 3/5] pnv/xive2: Allow writes to the Physical Thread Enable registers Frederic Barrat
2023-06-01 12:13 ` [PATCH v2 4/5] pnv/xive2: Introduce macros to manipulate TIMA addresses Frederic Barrat
2023-06-01 12:22   ` Cédric Le Goater
2023-06-01 12:13 ` [PATCH v2 5/5] pnv/xive2: Handle TIMA access through all ports Frederic Barrat
2023-06-01 12:25   ` Cédric Le Goater
2023-06-01 20:30 ` [PATCH v2 0/5] Various xive fixes Daniel Henrique Barboza

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