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From: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
To: <xen-devel@lists.xenproject.org>
Cc: <sstabellini@kernel.org>, <stefano.stabellini@amd.com>,
	<julien@xen.org>, <Volodymyr_Babchuk@epam.com>,
	<bertrand.marquis@arm.com>, <andrew.cooper3@citrix.com>,
	<george.dunlap@citrix.com>, <jbeulich@suse.com>, <wl@xen.org>,
	<rahul.singh@arm.com>,
	Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Subject: [XEN v8 5/5] xen/arm: p2m: Enable support for 32bit IPA for ARM_32
Date: Fri, 2 Jun 2023 13:07:54 +0100	[thread overview]
Message-ID: <20230602120754.23817-6-ayan.kumar.halder@amd.com> (raw)
In-Reply-To: <20230602120754.23817-1-ayan.kumar.halder@amd.com>

Refer ARM DDI 0406C.d ID040418, B3-1345,

"A stage 2 translation with an input address range of 31-34 bits can
start the translation either:

- With a first-level lookup, accessing a first-level translation
  table with 2-16 entries.

- With a second-level lookup, accessing a set of concatenated
  second-level translation tables"

Thus, for 32 bit IPA, there will be no concatenated root level tables.
So, the root-order is 0.

Also, Refer ARM DDI 0406C.d ID040418, B3-1348
"Determining the required first lookup level for stage 2 translations

For a stage 2 translation, the output address range from the stage 1
translations determines the required input address range for the stage 2
translation. The permitted values of VTCR.SL0 are:
0b00 Stage 2 translation lookup must start at the second level.
0b01 Stage 2 translation lookup must start at the first level.

VTCR.T0SZ must indicate the required input address range. The size of
the input address region is 2^(32-T0SZ) bytes."

Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of
input address region is 2^32 bytes.

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
---
Changes from -

v1 - New patch.

v2 - 1. Added Ack.

v3 - 1. Dropped Ack. 
2. Rebased the patch based on the previous change.

v4 - 1. t0sz is 0 for 32-bit IPA on Arm32.
2. Updated the commit message to explain t0sz, sl0 and root_order.

v5 - 1. Rebased on top of the changes in the previous patch.

v6 - 1. Removed the index for ARM_32.

v7 - 1. No changes.

 xen/arch/arm/p2m.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index 76388ba54b..a969068a68 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -2265,6 +2265,7 @@ void __init setup_virt_paging(void)
         [6] = { 52,      12/*12*/,  4,          2 },
         [7] = { 0 }  /* Invalid */
 #else
+        { 32,      0/*0*/,    0,          1 },
         { 40,      24/*24*/,  1,          1 }
 #endif
     };
-- 
2.17.1



  parent reply	other threads:[~2023-06-02 12:10 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-02 12:07 [XEN v8 0/5] Add support for 32-bit physical address Ayan Kumar Halder
2023-06-02 12:07 ` [XEN v8 1/5] xen/arm: p2m: Use the pa_range_info table to support ARM_32 and ARM_64 Ayan Kumar Halder
2023-06-15  8:05   ` Michal Orzel
2023-06-15  9:29     ` Ayan Kumar Halder
2023-06-15  9:40       ` Julien Grall
2023-06-15 10:25         ` Ayan Kumar Halder
2023-06-15 20:32     ` Julien Grall
2023-06-16  7:59       ` Michal Orzel
2023-06-16 20:37         ` Julien Grall
2023-06-16 20:30     ` Julien Grall
2023-06-02 12:07 ` [XEN v8 2/5] xen/arm: Introduce choice to enable 64/32 bit physical addressing Ayan Kumar Halder
2023-06-15 20:26   ` Julien Grall
2023-06-02 12:07 ` [XEN v8 3/5] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32" Ayan Kumar Halder
2023-06-02 12:07 ` [XEN v8 4/5] xen/arm: Restrict zeroeth_table_offset for ARM_64 Ayan Kumar Halder
2023-06-02 12:07 ` Ayan Kumar Halder [this message]
2023-06-15  8:07   ` [XEN v8 5/5] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Michal Orzel
2023-06-15 20:28   ` Julien Grall

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