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From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Frank Rowand <frowand.list@gmail.com>
Cc: Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>,
	Saravana Kannan <saravanak@google.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, iommu@lists.linux.dev,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v4 01/10] RISC-V: Add riscv_fw_parent_hartid() function
Date: Tue, 13 Jun 2023 21:04:06 +0530	[thread overview]
Message-ID: <20230613153415.350528-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230613153415.350528-1-apatel@ventanamicro.com>

We add common riscv_fw_parent_hartid() which help device drivers
to get parent hartid of the INTC (i.e. local interrupt controller)
fwnode. This should work for both DT and ACPI.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/processor.h |  3 +++
 arch/riscv/kernel/cpu.c            | 16 ++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 94a0590c6971..6fb8bbec8459 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -77,6 +77,9 @@ struct device_node;
 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 
+struct fwnode_handle;
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid);
+
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 5de6fb703cc2..67b335789b22 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -73,6 +73,22 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 	return -1;
 }
 
+/* Find hart ID of the CPU fwnode under which given fwnode falls. */
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid)
+{
+	int rc;
+	u64 temp;
+
+	if (!is_of_node(node)) {
+		rc = fwnode_property_read_u64_array(node, "hartid", &temp, 1);
+		if (!rc)
+			*hartid = temp;
+	} else
+		rc = riscv_of_parent_hartid(to_of_node(node), hartid);
+
+	return rc;
+}
+
 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Frank Rowand <frowand.list@gmail.com>
Cc: Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>,
	Saravana Kannan <saravanak@google.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, iommu@lists.linux.dev,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v4 01/10] RISC-V: Add riscv_fw_parent_hartid() function
Date: Tue, 13 Jun 2023 21:04:06 +0530	[thread overview]
Message-ID: <20230613153415.350528-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230613153415.350528-1-apatel@ventanamicro.com>

We add common riscv_fw_parent_hartid() which help device drivers
to get parent hartid of the INTC (i.e. local interrupt controller)
fwnode. This should work for both DT and ACPI.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/processor.h |  3 +++
 arch/riscv/kernel/cpu.c            | 16 ++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 94a0590c6971..6fb8bbec8459 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -77,6 +77,9 @@ struct device_node;
 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 
+struct fwnode_handle;
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid);
+
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 5de6fb703cc2..67b335789b22 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -73,6 +73,22 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 	return -1;
 }
 
+/* Find hart ID of the CPU fwnode under which given fwnode falls. */
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid)
+{
+	int rc;
+	u64 temp;
+
+	if (!is_of_node(node)) {
+		rc = fwnode_property_read_u64_array(node, "hartid", &temp, 1);
+		if (!rc)
+			*hartid = temp;
+	} else
+		rc = riscv_of_parent_hartid(to_of_node(node), hartid);
+
+	return rc;
+}
+
 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
-- 
2.34.1


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  reply	other threads:[~2023-06-13 15:34 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-13 15:34 [PATCH v4 00/10] Linux RISC-V AIA Support Anup Patel
2023-06-13 15:34 ` Anup Patel
2023-06-13 15:34 ` Anup Patel [this message]
2023-06-13 15:34   ` [PATCH v4 01/10] RISC-V: Add riscv_fw_parent_hartid() function Anup Patel
2023-06-13 15:34 ` [PATCH v4 02/10] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 03/10] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 04/10] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 05/10] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 06/10] irqchip/riscv-imsic: Improve IOMMU DMA support Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-14 14:46   ` Jason Gunthorpe
2023-06-14 14:46     ` Jason Gunthorpe
2023-06-14 16:17     ` Anup Patel
2023-06-14 16:17       ` Anup Patel
2023-06-14 16:50       ` Jason Gunthorpe
2023-06-14 16:50         ` Jason Gunthorpe
2023-06-15  5:46         ` Anup Patel
2023-06-15  5:46           ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 07/10] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-14 19:27   ` Conor Dooley
2023-06-14 19:27     ` Conor Dooley
2023-06-15  5:47     ` Anup Patel
2023-06-15  5:47       ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 08/10] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-15 19:17   ` Saravana Kannan
2023-06-15 19:17     ` Saravana Kannan
2023-06-15 19:31     ` Conor Dooley
2023-06-15 19:31       ` Conor Dooley
2023-06-15 20:45       ` Saravana Kannan
2023-06-15 20:45         ` Saravana Kannan
2023-06-15 21:11         ` Conor Dooley
2023-06-15 21:11           ` Conor Dooley
2023-06-16  2:01     ` Anup Patel
2023-06-16  2:01       ` Anup Patel
2023-06-16 22:05       ` Saravana Kannan
2023-06-16 22:05         ` Saravana Kannan
2023-06-19  6:13         ` Anup Patel
2023-06-19  6:13           ` Anup Patel
2023-06-22 20:56           ` Saravana Kannan
2023-06-22 20:56             ` Saravana Kannan
2023-06-23 11:47             ` Anup Patel
2023-06-23 11:47               ` Anup Patel
2023-06-23 12:49               ` Marc Zyngier
2023-06-23 12:49                 ` Marc Zyngier
2023-06-23 13:52                 ` Anup Patel
2023-06-23 13:52                   ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 09/10] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-06-13 15:34   ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 10/10] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-06-13 15:34   ` Anup Patel

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