[PATCH 0/4] target/ppc: Fixes for instruction-related

[Nicholas Piggin <npiggin@gmail.com>]

Because they got more complexities than I first thought, these patches
are broken out from the bigger series here:

https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00425.html

Since then I fixed the --disable-tcg compile bug reported by Anushree
hopefully. Also added a workaround for KVM so injected interrupts
wouldn't attempt to find the prefix bit setting. I don't know how much
that is really needed, but injection callers would have to set it one
way or anohter if we need to add it.

Thanks,
Nick

Nicholas Piggin (4):
  target/ppc: Fix instruction loading endianness in alignment interrupt
  target/ppc: Change partition-scope translate interface
  target/ppc: Add SRR1 prefix indication to interrupt handlers
  target/ppc: Implement HEIR SPR

 target/ppc/cpu.h         |   1 +
 target/ppc/cpu_init.c    |  23 ++++++++
 target/ppc/excp_helper.c | 110 ++++++++++++++++++++++++++++++++++++++-
 target/ppc/mmu-radix64.c |  38 ++++++++++----
 4 files changed, 159 insertions(+), 13 deletions(-)

-- 
2.40.1